Lines Matching full:arm
16 #include "ARM.h"
32 #define DEBUG_TYPE "arm-pseudo"
35 VerifyARMPseudo("verify-arm-pseudo-expand", cl::Hidden,
36 cl::desc("Verify machine code after expanding ARM pseudos"));
38 #define ARM_EXPAND_PSEUDO_NAME "ARM pseudo instruction expansion pass"
171 { ARM::VLD1LNq16Pseudo, ARM::VLD1LNd16, true, false, false, EvenDblSpc, 1, 4 ,true},
172 { ARM::VLD1LNq16Pseudo_UPD, ARM::VLD1LNd16_UPD, true, true, true, EvenDblSpc, 1, 4 ,true},
173 { ARM::VLD1LNq32Pseudo, ARM::VLD1LNd32, true, false, false, EvenDblSpc, 1, 2 ,true},
174 { ARM::VLD1LNq32Pseudo_UPD, ARM::VLD1LNd32_UPD, true, true, true, EvenDblSpc, 1, 2 ,true},
175 { ARM::VLD1LNq8Pseudo, ARM::VLD1LNd8, true, false, false, EvenDblSpc, 1, 8 ,true},
176 { ARM::VLD1LNq8Pseudo_UPD, ARM::VLD1LNd8_UPD, true, true, true, EvenDblSpc, 1, 8 ,true},
178 { ARM::VLD1d16QPseudo, ARM::VLD1d16Q, true, false, false, SingleSpc, 4, 4 ,false},
179 { ARM::VLD1d16QPseudoWB_fixed, ARM::VLD1d16Qwb_fixed, true, true, false, SingleSpc, 4, 4 ,false…
180 { ARM::VLD1d16QPseudoWB_register, ARM::VLD1d16Qwb_register, true, true, true, SingleSpc, 4, 4 ,fa…
181 { ARM::VLD1d16TPseudo, ARM::VLD1d16T, true, false, false, SingleSpc, 3, 4 ,false},
182 { ARM::VLD1d16TPseudoWB_fixed, ARM::VLD1d16Twb_fixed, true, true, false, SingleSpc, 3, 4 ,false…
183 { ARM::VLD1d16TPseudoWB_register, ARM::VLD1d16Twb_register, true, true, true, SingleSpc, 3, 4 ,fa…
185 { ARM::VLD1d32QPseudo, ARM::VLD1d32Q, true, false, false, SingleSpc, 4, 2 ,false},
186 { ARM::VLD1d32QPseudoWB_fixed, ARM::VLD1d32Qwb_fixed, true, true, false, SingleSpc, 4, 2 ,false…
187 { ARM::VLD1d32QPseudoWB_register, ARM::VLD1d32Qwb_register, true, true, true, SingleSpc, 4, 2 ,fa…
188 { ARM::VLD1d32TPseudo, ARM::VLD1d32T, true, false, false, SingleSpc, 3, 2 ,false},
189 { ARM::VLD1d32TPseudoWB_fixed, ARM::VLD1d32Twb_fixed, true, true, false, SingleSpc, 3, 2 ,false…
190 { ARM::VLD1d32TPseudoWB_register, ARM::VLD1d32Twb_register, true, true, true, SingleSpc, 3, 2 ,fa…
192 { ARM::VLD1d64QPseudo, ARM::VLD1d64Q, true, false, false, SingleSpc, 4, 1 ,false},
193 { ARM::VLD1d64QPseudoWB_fixed, ARM::VLD1d64Qwb_fixed, true, true, false, SingleSpc, 4, 1 ,fals…
194 { ARM::VLD1d64QPseudoWB_register, ARM::VLD1d64Qwb_register, true, true, true, SingleSpc, 4, 1 …
195 { ARM::VLD1d64TPseudo, ARM::VLD1d64T, true, false, false, SingleSpc, 3, 1 ,false},
196 { ARM::VLD1d64TPseudoWB_fixed, ARM::VLD1d64Twb_fixed, true, true, false, SingleSpc, 3, 1 ,fals…
197 { ARM::VLD1d64TPseudoWB_register, ARM::VLD1d64Twb_register, true, true, true, SingleSpc, 3, 1 ,f…
199 { ARM::VLD1d8QPseudo, ARM::VLD1d8Q, true, false, false, SingleSpc, 4, 8 ,false},
200 { ARM::VLD1d8QPseudoWB_fixed, ARM::VLD1d8Qwb_fixed, true, true, false, SingleSpc, 4, 8 ,fals…
201 { ARM::VLD1d8QPseudoWB_register, ARM::VLD1d8Qwb_register, true, true, true, SingleSpc, 4, 8 ,fa…
202 { ARM::VLD1d8TPseudo, ARM::VLD1d8T, true, false, false, SingleSpc, 3, 8 ,false},
203 { ARM::VLD1d8TPseudoWB_fixed, ARM::VLD1d8Twb_fixed, true, true, false, SingleSpc, 3, 8 ,fals…
204 { ARM::VLD1d8TPseudoWB_register, ARM::VLD1d8Twb_register, true, true, true, SingleSpc, 3, 8 ,f…
206 { ARM::VLD1q16HighQPseudo, ARM::VLD1d16Q, true, false, false, SingleHighQSpc, 4, 4 ,false},
207 { ARM::VLD1q16HighQPseudo_UPD, ARM::VLD1d16Qwb_fixed, true, true, true, SingleHighQSpc, 4, 4 ,f…
208 { ARM::VLD1q16HighTPseudo, ARM::VLD1d16T, true, false, false, SingleHighTSpc, 3, 4 ,false},
209 { ARM::VLD1q16HighTPseudo_UPD, ARM::VLD1d16Twb_fixed, true, true, true, SingleHighTSpc, 3, 4 ,f…
210 { ARM::VLD1q16LowQPseudo_UPD, ARM::VLD1d16Qwb_fixed, true, true, true, SingleLowSpc, 4, 4 ,fal…
211 { ARM::VLD1q16LowTPseudo_UPD, ARM::VLD1d16Twb_fixed, true, true, true, SingleLowSpc, 3, 4 ,fal…
213 { ARM::VLD1q32HighQPseudo, ARM::VLD1d32Q, true, false, false, SingleHighQSpc, 4, 2 ,false},
214 { ARM::VLD1q32HighQPseudo_UPD, ARM::VLD1d32Qwb_fixed, true, true, true, SingleHighQSpc, 4, 2 ,f…
215 { ARM::VLD1q32HighTPseudo, ARM::VLD1d32T, true, false, false, SingleHighTSpc, 3, 2 ,false},
216 { ARM::VLD1q32HighTPseudo_UPD, ARM::VLD1d32Twb_fixed, true, true, true, SingleHighTSpc, 3, 2 ,f…
217 { ARM::VLD1q32LowQPseudo_UPD, ARM::VLD1d32Qwb_fixed, true, true, true, SingleLowSpc, 4, 2 ,fal…
218 { ARM::VLD1q32LowTPseudo_UPD, ARM::VLD1d32Twb_fixed, true, true, true, SingleLowSpc, 3, 2 ,fal…
220 { ARM::VLD1q64HighQPseudo, ARM::VLD1d64Q, true, false, false, SingleHighQSpc, 4, 1 ,false},
221 { ARM::VLD1q64HighQPseudo_UPD, ARM::VLD1d64Qwb_fixed, true, true, true, SingleHighQSpc, 4, 1 ,f…
222 { ARM::VLD1q64HighTPseudo, ARM::VLD1d64T, true, false, false, SingleHighTSpc, 3, 1 ,false},
223 { ARM::VLD1q64HighTPseudo_UPD, ARM::VLD1d64Twb_fixed, true, true, true, SingleHighTSpc, 3, 1 ,f…
224 { ARM::VLD1q64LowQPseudo_UPD, ARM::VLD1d64Qwb_fixed, true, true, true, SingleLowSpc, 4, 1 ,fal…
225 { ARM::VLD1q64LowTPseudo_UPD, ARM::VLD1d64Twb_fixed, true, true, true, SingleLowSpc, 3, 1 ,fal…
227 { ARM::VLD1q8HighQPseudo, ARM::VLD1d8Q, true, false, false, SingleHighQSpc, 4, 8 ,false},
228 { ARM::VLD1q8HighQPseudo_UPD, ARM::VLD1d8Qwb_fixed, true, true, true, SingleHighQSpc, 4, 8 ,fal…
229 { ARM::VLD1q8HighTPseudo, ARM::VLD1d8T, true, false, false, SingleHighTSpc, 3, 8 ,false},
230 { ARM::VLD1q8HighTPseudo_UPD, ARM::VLD1d8Twb_fixed, true, true, true, SingleHighTSpc, 3, 8 ,fal…
231 { ARM::VLD1q8LowQPseudo_UPD, ARM::VLD1d8Qwb_fixed, true, true, true, SingleLowSpc, 4, 8 ,false…
232 { ARM::VLD1q8LowTPseudo_UPD, ARM::VLD1d8Twb_fixed, true, true, true, SingleLowSpc, 3, 8 ,false…
234 { ARM::VLD2DUPq16EvenPseudo, ARM::VLD2DUPd16x2, true, false, false, EvenDblSpc, 2, 4 ,false},
235 { ARM::VLD2DUPq16OddPseudo, ARM::VLD2DUPd16x2, true, false, false, OddDblSpc, 2, 4 ,false},
236 { ARM::VLD2DUPq16OddPseudoWB_fixed, ARM::VLD2DUPd16x2wb_fixed, true, true, false, OddDblSpc, 2, …
237 { ARM::VLD2DUPq16OddPseudoWB_register, ARM::VLD2DUPd16x2wb_register, true, true, true, OddDblSpc,…
238 { ARM::VLD2DUPq32EvenPseudo, ARM::VLD2DUPd32x2, true, false, false, EvenDblSpc, 2, 2 ,false},
239 { ARM::VLD2DUPq32OddPseudo, ARM::VLD2DUPd32x2, true, false, false, OddDblSpc, 2, 2 ,false},
240 { ARM::VLD2DUPq32OddPseudoWB_fixed, ARM::VLD2DUPd32x2wb_fixed, true, true, false, OddDblSpc, 2, …
241 { ARM::VLD2DUPq32OddPseudoWB_register, ARM::VLD2DUPd32x2wb_register, true, true, true, OddDblSpc,…
242 { ARM::VLD2DUPq8EvenPseudo, ARM::VLD2DUPd8x2, true, false, false, EvenDblSpc, 2, 8 ,false},
243 { ARM::VLD2DUPq8OddPseudo, ARM::VLD2DUPd8x2, true, false, false, OddDblSpc, 2, 8 ,false},
244 { ARM::VLD2DUPq8OddPseudoWB_fixed, ARM::VLD2DUPd8x2wb_fixed, true, true, false, OddDblSpc, 2, 8…
245 { ARM::VLD2DUPq8OddPseudoWB_register, ARM::VLD2DUPd8x2wb_register, true, true, true, OddDblSpc, …
247 { ARM::VLD2LNd16Pseudo, ARM::VLD2LNd16, true, false, false, SingleSpc, 2, 4 ,true},
248 { ARM::VLD2LNd16Pseudo_UPD, ARM::VLD2LNd16_UPD, true, true, true, SingleSpc, 2, 4 ,true},
249 { ARM::VLD2LNd32Pseudo, ARM::VLD2LNd32, true, false, false, SingleSpc, 2, 2 ,true},
250 { ARM::VLD2LNd32Pseudo_UPD, ARM::VLD2LNd32_UPD, true, true, true, SingleSpc, 2, 2 ,true},
251 { ARM::VLD2LNd8Pseudo, ARM::VLD2LNd8, true, false, false, SingleSpc, 2, 8 ,true},
252 { ARM::VLD2LNd8Pseudo_UPD, ARM::VLD2LNd8_UPD, true, true, true, SingleSpc, 2, 8 ,true},
253 { ARM::VLD2LNq16Pseudo, ARM::VLD2LNq16, true, false, false, EvenDblSpc, 2, 4 ,true},
254 { ARM::VLD2LNq16Pseudo_UPD, ARM::VLD2LNq16_UPD, true, true, true, EvenDblSpc, 2, 4 ,true},
255 { ARM::VLD2LNq32Pseudo, ARM::VLD2LNq32, true, false, false, EvenDblSpc, 2, 2 ,true},
256 { ARM::VLD2LNq32Pseudo_UPD, ARM::VLD2LNq32_UPD, true, true, true, EvenDblSpc, 2, 2 ,true},
258 { ARM::VLD2q16Pseudo, ARM::VLD2q16, true, false, false, SingleSpc, 4, 4 ,false},
259 { ARM::VLD2q16PseudoWB_fixed, ARM::VLD2q16wb_fixed, true, true, false, SingleSpc, 4, 4 ,false},
260 { ARM::VLD2q16PseudoWB_register, ARM::VLD2q16wb_register, true, true, true, SingleSpc, 4, 4 ,fa…
261 { ARM::VLD2q32Pseudo, ARM::VLD2q32, true, false, false, SingleSpc, 4, 2 ,false},
262 { ARM::VLD2q32PseudoWB_fixed, ARM::VLD2q32wb_fixed, true, true, false, SingleSpc, 4, 2 ,false},
263 { ARM::VLD2q32PseudoWB_register, ARM::VLD2q32wb_register, true, true, true, SingleSpc, 4, 2 ,fa…
264 { ARM::VLD2q8Pseudo, ARM::VLD2q8, true, false, false, SingleSpc, 4, 8 ,false},
265 { ARM::VLD2q8PseudoWB_fixed, ARM::VLD2q8wb_fixed, true, true, false, SingleSpc, 4, 8 ,false},
266 { ARM::VLD2q8PseudoWB_register, ARM::VLD2q8wb_register, true, true, true, SingleSpc, 4, 8 ,fal…
268 { ARM::VLD3DUPd16Pseudo, ARM::VLD3DUPd16, true, false, false, SingleSpc, 3, 4,true},
269 { ARM::VLD3DUPd16Pseudo_UPD, ARM::VLD3DUPd16_UPD, true, true, true, SingleSpc, 3, 4,true},
270 { ARM::VLD3DUPd32Pseudo, ARM::VLD3DUPd32, true, false, false, SingleSpc, 3, 2,true},
271 { ARM::VLD3DUPd32Pseudo_UPD, ARM::VLD3DUPd32_UPD, true, true, true, SingleSpc, 3, 2,true},
272 { ARM::VLD3DUPd8Pseudo, ARM::VLD3DUPd8, true, false, false, SingleSpc, 3, 8,true},
273 { ARM::VLD3DUPd8Pseudo_UPD, ARM::VLD3DUPd8_UPD, true, true, true, SingleSpc, 3, 8,true},
274 { ARM::VLD3DUPq16EvenPseudo, ARM::VLD3DUPq16, true, false, false, EvenDblSpc, 3, 4 ,true},
275 { ARM::VLD3DUPq16OddPseudo, ARM::VLD3DUPq16, true, false, false, OddDblSpc, 3, 4 ,true},
276 { ARM::VLD3DUPq16OddPseudo_UPD, ARM::VLD3DUPq16_UPD, true, true, true, OddDblSpc, 3, 4 ,true},
277 { ARM::VLD3DUPq32EvenPseudo, ARM::VLD3DUPq32, true, false, false, EvenDblSpc, 3, 2 ,true},
278 { ARM::VLD3DUPq32OddPseudo, ARM::VLD3DUPq32, true, false, false, OddDblSpc, 3, 2 ,true},
279 { ARM::VLD3DUPq32OddPseudo_UPD, ARM::VLD3DUPq32_UPD, true, true, true, OddDblSpc, 3, 2 ,true},
280 { ARM::VLD3DUPq8EvenPseudo, ARM::VLD3DUPq8, true, false, false, EvenDblSpc, 3, 8 ,true},
281 { ARM::VLD3DUPq8OddPseudo, ARM::VLD3DUPq8, true, false, false, OddDblSpc, 3, 8 ,true},
282 { ARM::VLD3DUPq8OddPseudo_UPD, ARM::VLD3DUPq8_UPD, true, true, true, OddDblSpc, 3, 8 ,true},
284 { ARM::VLD3LNd16Pseudo, ARM::VLD3LNd16, true, false, false, SingleSpc, 3, 4 ,true},
285 { ARM::VLD3LNd16Pseudo_UPD, ARM::VLD3LNd16_UPD, true, true, true, SingleSpc, 3, 4 ,true},
286 { ARM::VLD3LNd32Pseudo, ARM::VLD3LNd32, true, false, false, SingleSpc, 3, 2 ,true},
287 { ARM::VLD3LNd32Pseudo_UPD, ARM::VLD3LNd32_UPD, true, true, true, SingleSpc, 3, 2 ,true},
288 { ARM::VLD3LNd8Pseudo, ARM::VLD3LNd8, true, false, false, SingleSpc, 3, 8 ,true},
289 { ARM::VLD3LNd8Pseudo_UPD, ARM::VLD3LNd8_UPD, true, true, true, SingleSpc, 3, 8 ,true},
290 { ARM::VLD3LNq16Pseudo, ARM::VLD3LNq16, true, false, false, EvenDblSpc, 3, 4 ,true},
291 { ARM::VLD3LNq16Pseudo_UPD, ARM::VLD3LNq16_UPD, true, true, true, EvenDblSpc, 3, 4 ,true},
292 { ARM::VLD3LNq32Pseudo, ARM::VLD3LNq32, true, false, false, EvenDblSpc, 3, 2 ,true},
293 { ARM::VLD3LNq32Pseudo_UPD, ARM::VLD3LNq32_UPD, true, true, true, EvenDblSpc, 3, 2 ,true},
295 { ARM::VLD3d16Pseudo, ARM::VLD3d16, true, false, false, SingleSpc, 3, 4 ,true},
296 { ARM::VLD3d16Pseudo_UPD, ARM::VLD3d16_UPD, true, true, true, SingleSpc, 3, 4 ,true},
297 { ARM::VLD3d32Pseudo, ARM::VLD3d32, true, false, false, SingleSpc, 3, 2 ,true},
298 { ARM::VLD3d32Pseudo_UPD, ARM::VLD3d32_UPD, true, true, true, SingleSpc, 3, 2 ,true},
299 { ARM::VLD3d8Pseudo, ARM::VLD3d8, true, false, false, SingleSpc, 3, 8 ,true},
300 { ARM::VLD3d8Pseudo_UPD, ARM::VLD3d8_UPD, true, true, true, SingleSpc, 3, 8 ,true},
302 { ARM::VLD3q16Pseudo_UPD, ARM::VLD3q16_UPD, true, true, true, EvenDblSpc, 3, 4 ,true},
303 { ARM::VLD3q16oddPseudo, ARM::VLD3q16, true, false, false, OddDblSpc, 3, 4 ,true},
304 { ARM::VLD3q16oddPseudo_UPD, ARM::VLD3q16_UPD, true, true, true, OddDblSpc, 3, 4 ,true},
305 { ARM::VLD3q32Pseudo_UPD, ARM::VLD3q32_UPD, true, true, true, EvenDblSpc, 3, 2 ,true},
306 { ARM::VLD3q32oddPseudo, ARM::VLD3q32, true, false, false, OddDblSpc, 3, 2 ,true},
307 { ARM::VLD3q32oddPseudo_UPD, ARM::VLD3q32_UPD, true, true, true, OddDblSpc, 3, 2 ,true},
308 { ARM::VLD3q8Pseudo_UPD, ARM::VLD3q8_UPD, true, true, true, EvenDblSpc, 3, 8 ,true},
309 { ARM::VLD3q8oddPseudo, ARM::VLD3q8, true, false, false, OddDblSpc, 3, 8 ,true},
310 { ARM::VLD3q8oddPseudo_UPD, ARM::VLD3q8_UPD, true, true, true, OddDblSpc, 3, 8 ,true},
312 { ARM::VLD4DUPd16Pseudo, ARM::VLD4DUPd16, true, false, false, SingleSpc, 4, 4,true},
313 { ARM::VLD4DUPd16Pseudo_UPD, ARM::VLD4DUPd16_UPD, true, true, true, SingleSpc, 4, 4,true},
314 { ARM::VLD4DUPd32Pseudo, ARM::VLD4DUPd32, true, false, false, SingleSpc, 4, 2,true},
315 { ARM::VLD4DUPd32Pseudo_UPD, ARM::VLD4DUPd32_UPD, true, true, true, SingleSpc, 4, 2,true},
316 { ARM::VLD4DUPd8Pseudo, ARM::VLD4DUPd8, true, false, false, SingleSpc, 4, 8,true},
317 { ARM::VLD4DUPd8Pseudo_UPD, ARM::VLD4DUPd8_UPD, true, true, true, SingleSpc, 4, 8,true},
318 { ARM::VLD4DUPq16EvenPseudo, ARM::VLD4DUPq16, true, false, false, EvenDblSpc, 4, 4 ,true},
319 { ARM::VLD4DUPq16OddPseudo, ARM::VLD4DUPq16, true, false, false, OddDblSpc, 4, 4 ,true},
320 { ARM::VLD4DUPq16OddPseudo_UPD, ARM::VLD4DUPq16_UPD, true, true, true, OddDblSpc, 4, 4 ,true},
321 { ARM::VLD4DUPq32EvenPseudo, ARM::VLD4DUPq32, true, false, false, EvenDblSpc, 4, 2 ,true},
322 { ARM::VLD4DUPq32OddPseudo, ARM::VLD4DUPq32, true, false, false, OddDblSpc, 4, 2 ,true},
323 { ARM::VLD4DUPq32OddPseudo_UPD, ARM::VLD4DUPq32_UPD, true, true, true, OddDblSpc, 4, 2 ,true},
324 { ARM::VLD4DUPq8EvenPseudo, ARM::VLD4DUPq8, true, false, false, EvenDblSpc, 4, 8 ,true},
325 { ARM::VLD4DUPq8OddPseudo, ARM::VLD4DUPq8, true, false, false, OddDblSpc, 4, 8 ,true},
326 { ARM::VLD4DUPq8OddPseudo_UPD, ARM::VLD4DUPq8_UPD, true, true, true, OddDblSpc, 4, 8 ,true},
328 { ARM::VLD4LNd16Pseudo, ARM::VLD4LNd16, true, false, false, SingleSpc, 4, 4 ,true},
329 { ARM::VLD4LNd16Pseudo_UPD, ARM::VLD4LNd16_UPD, true, true, true, SingleSpc, 4, 4 ,true},
330 { ARM::VLD4LNd32Pseudo, ARM::VLD4LNd32, true, false, false, SingleSpc, 4, 2 ,true},
331 { ARM::VLD4LNd32Pseudo_UPD, ARM::VLD4LNd32_UPD, true, true, true, SingleSpc, 4, 2 ,true},
332 { ARM::VLD4LNd8Pseudo, ARM::VLD4LNd8, true, false, false, SingleSpc, 4, 8 ,true},
333 { ARM::VLD4LNd8Pseudo_UPD, ARM::VLD4LNd8_UPD, true, true, true, SingleSpc, 4, 8 ,true},
334 { ARM::VLD4LNq16Pseudo, ARM::VLD4LNq16, true, false, false, EvenDblSpc, 4, 4 ,true},
335 { ARM::VLD4LNq16Pseudo_UPD, ARM::VLD4LNq16_UPD, true, true, true, EvenDblSpc, 4, 4 ,true},
336 { ARM::VLD4LNq32Pseudo, ARM::VLD4LNq32, true, false, false, EvenDblSpc, 4, 2 ,true},
337 { ARM::VLD4LNq32Pseudo_UPD, ARM::VLD4LNq32_UPD, true, true, true, EvenDblSpc, 4, 2 ,true},
339 { ARM::VLD4d16Pseudo, ARM::VLD4d16, true, false, false, SingleSpc, 4, 4 ,true},
340 { ARM::VLD4d16Pseudo_UPD, ARM::VLD4d16_UPD, true, true, true, SingleSpc, 4, 4 ,true},
341 { ARM::VLD4d32Pseudo, ARM::VLD4d32, true, false, false, SingleSpc, 4, 2 ,true},
342 { ARM::VLD4d32Pseudo_UPD, ARM::VLD4d32_UPD, true, true, true, SingleSpc, 4, 2 ,true},
343 { ARM::VLD4d8Pseudo, ARM::VLD4d8, true, false, false, SingleSpc, 4, 8 ,true},
344 { ARM::VLD4d8Pseudo_UPD, ARM::VLD4d8_UPD, true, true, true, SingleSpc, 4, 8 ,true},
346 { ARM::VLD4q16Pseudo_UPD, ARM::VLD4q16_UPD, true, true, true, EvenDblSpc, 4, 4 ,true},
347 { ARM::VLD4q16oddPseudo, ARM::VLD4q16, true, false, false, OddDblSpc, 4, 4 ,true},
348 { ARM::VLD4q16oddPseudo_UPD, ARM::VLD4q16_UPD, true, true, true, OddDblSpc, 4, 4 ,true},
349 { ARM::VLD4q32Pseudo_UPD, ARM::VLD4q32_UPD, true, true, true, EvenDblSpc, 4, 2 ,true},
350 { ARM::VLD4q32oddPseudo, ARM::VLD4q32, true, false, false, OddDblSpc, 4, 2 ,true},
351 { ARM::VLD4q32oddPseudo_UPD, ARM::VLD4q32_UPD, true, true, true, OddDblSpc, 4, 2 ,true},
352 { ARM::VLD4q8Pseudo_UPD, ARM::VLD4q8_UPD, true, true, true, EvenDblSpc, 4, 8 ,true},
353 { ARM::VLD4q8oddPseudo, ARM::VLD4q8, true, false, false, OddDblSpc, 4, 8 ,true},
354 { ARM::VLD4q8oddPseudo_UPD, ARM::VLD4q8_UPD, true, true, true, OddDblSpc, 4, 8 ,true},
356 { ARM::VST1LNq16Pseudo, ARM::VST1LNd16, false, false, false, EvenDblSpc, 1, 4 ,true},
357 { ARM::VST1LNq16Pseudo_UPD, ARM::VST1LNd16_UPD, false, true, true, EvenDblSpc, 1, 4 ,true},
358 { ARM::VST1LNq32Pseudo, ARM::VST1LNd32, false, false, false, EvenDblSpc, 1, 2 ,true},
359 { ARM::VST1LNq32Pseudo_UPD, ARM::VST1LNd32_UPD, false, true, true, EvenDblSpc, 1, 2 ,true},
360 { ARM::VST1LNq8Pseudo, ARM::VST1LNd8, false, false, false, EvenDblSpc, 1, 8 ,true},
361 { ARM::VST1LNq8Pseudo_UPD, ARM::VST1LNd8_UPD, false, true, true, EvenDblSpc, 1, 8 ,true},
363 { ARM::VST1d16QPseudo, ARM::VST1d16Q, false, false, false, SingleSpc, 4, 4 ,false},
364 { ARM::VST1d16QPseudoWB_fixed, ARM::VST1d16Qwb_fixed, false, true, false, SingleSpc, 4, 4 ,false},
365 { ARM::VST1d16QPseudoWB_register, ARM::VST1d16Qwb_register, false, true, true, SingleSpc, 4, 4 ,fa…
366 { ARM::VST1d16TPseudo, ARM::VST1d16T, false, false, false, SingleSpc, 3, 4 ,false},
367 { ARM::VST1d16TPseudoWB_fixed, ARM::VST1d16Twb_fixed, false, true, false, SingleSpc, 3, 4 ,false},
368 { ARM::VST1d16TPseudoWB_register, ARM::VST1d16Twb_register, false, true, true, SingleSpc, 3, 4 ,fa…
370 { ARM::VST1d32QPseudo, ARM::VST1d32Q, false, false, false, SingleSpc, 4, 2 ,false},
371 { ARM::VST1d32QPseudoWB_fixed, ARM::VST1d32Qwb_fixed, false, true, false, SingleSpc, 4, 2 ,false},
372 { ARM::VST1d32QPseudoWB_register, ARM::VST1d32Qwb_register, false, true, true, SingleSpc, 4, 2 ,fa…
373 { ARM::VST1d32TPseudo, ARM::VST1d32T, false, false, false, SingleSpc, 3, 2 ,false},
374 { ARM::VST1d32TPseudoWB_fixed, ARM::VST1d32Twb_fixed, false, true, false, SingleSpc, 3, 2 ,false},
375 { ARM::VST1d32TPseudoWB_register, ARM::VST1d32Twb_register, false, true, true, SingleSpc, 3, 2 ,fa…
377 { ARM::VST1d64QPseudo, ARM::VST1d64Q, false, false, false, SingleSpc, 4, 1 ,false},
378 { ARM::VST1d64QPseudoWB_fixed, ARM::VST1d64Qwb_fixed, false, true, false, SingleSpc, 4, 1 ,false…
379 { ARM::VST1d64QPseudoWB_register, ARM::VST1d64Qwb_register, false, true, true, SingleSpc, 4, 1 ,f…
380 { ARM::VST1d64TPseudo, ARM::VST1d64T, false, false, false, SingleSpc, 3, 1 ,false},
381 { ARM::VST1d64TPseudoWB_fixed, ARM::VST1d64Twb_fixed, false, true, false, SingleSpc, 3, 1 ,false…
382 { ARM::VST1d64TPseudoWB_register, ARM::VST1d64Twb_register, false, true, true, SingleSpc, 3, 1 ,f…
384 { ARM::VST1d8QPseudo, ARM::VST1d8Q, false, false, false, SingleSpc, 4, 8 ,false},
385 { ARM::VST1d8QPseudoWB_fixed, ARM::VST1d8Qwb_fixed, false, true, false, SingleSpc, 4, 8 ,false},
386 { ARM::VST1d8QPseudoWB_register, ARM::VST1d8Qwb_register, false, true, true, SingleSpc, 4, 8 ,fal…
387 { ARM::VST1d8TPseudo, ARM::VST1d8T, false, false, false, SingleSpc, 3, 8 ,false},
388 { ARM::VST1d8TPseudoWB_fixed, ARM::VST1d8Twb_fixed, false, true, false, SingleSpc, 3, 8 ,false},
389 { ARM::VST1d8TPseudoWB_register, ARM::VST1d8Twb_register, false, true, true, SingleSpc, 3, 8 ,fal…
391 { ARM::VST1q16HighQPseudo, ARM::VST1d16Q, false, false, false, SingleHighQSpc, 4, 4 ,false},
392 { ARM::VST1q16HighQPseudo_UPD, ARM::VST1d16Qwb_fixed, false, true, true, SingleHighQSpc, 4, 8 ,…
393 { ARM::VST1q16HighTPseudo, ARM::VST1d16T, false, false, false, SingleHighTSpc, 3, 4 ,false},
394 { ARM::VST1q16HighTPseudo_UPD, ARM::VST1d16Twb_fixed, false, true, true, SingleHighTSpc, 3, 4 ,…
395 { ARM::VST1q16LowQPseudo_UPD, ARM::VST1d16Qwb_fixed, false, true, true, SingleLowSpc, 4, 4 ,fa…
396 { ARM::VST1q16LowTPseudo_UPD, ARM::VST1d16Twb_fixed, false, true, true, SingleLowSpc, 3, 4 ,fa…
398 { ARM::VST1q32HighQPseudo, ARM::VST1d32Q, false, false, false, SingleHighQSpc, 4, 2 ,false},
399 { ARM::VST1q32HighQPseudo_UPD, ARM::VST1d32Qwb_fixed, false, true, true, SingleHighQSpc, 4, 8 ,…
400 { ARM::VST1q32HighTPseudo, ARM::VST1d32T, false, false, false, SingleHighTSpc, 3, 2 ,false},
401 { ARM::VST1q32HighTPseudo_UPD, ARM::VST1d32Twb_fixed, false, true, true, SingleHighTSpc, 3, 2 ,…
402 { ARM::VST1q32LowQPseudo_UPD, ARM::VST1d32Qwb_fixed, false, true, true, SingleLowSpc, 4, 2 ,fa…
403 { ARM::VST1q32LowTPseudo_UPD, ARM::VST1d32Twb_fixed, false, true, true, SingleLowSpc, 3, 2 ,fa…
405 { ARM::VST1q64HighQPseudo, ARM::VST1d64Q, false, false, false, SingleHighQSpc, 4, 1 ,false},
406 { ARM::VST1q64HighQPseudo_UPD, ARM::VST1d64Qwb_fixed, false, true, true, SingleHighQSpc, 4, 8 ,…
407 { ARM::VST1q64HighTPseudo, ARM::VST1d64T, false, false, false, SingleHighTSpc, 3, 1 ,false},
408 { ARM::VST1q64HighTPseudo_UPD, ARM::VST1d64Twb_fixed, false, true, true, SingleHighTSpc, 3, 1 ,…
409 { ARM::VST1q64LowQPseudo_UPD, ARM::VST1d64Qwb_fixed, false, true, true, SingleLowSpc, 4, 1 ,fa…
410 { ARM::VST1q64LowTPseudo_UPD, ARM::VST1d64Twb_fixed, false, true, true, SingleLowSpc, 3, 1 ,fa…
412 { ARM::VST1q8HighQPseudo, ARM::VST1d8Q, false, false, false, SingleHighQSpc, 4, 8 ,false},
413 { ARM::VST1q8HighQPseudo_UPD, ARM::VST1d8Qwb_fixed, false, true, true, SingleHighQSpc, 4, 8 ,fa…
414 { ARM::VST1q8HighTPseudo, ARM::VST1d8T, false, false, false, SingleHighTSpc, 3, 8 ,false},
415 { ARM::VST1q8HighTPseudo_UPD, ARM::VST1d8Twb_fixed, false, true, true, SingleHighTSpc, 3, 8 ,fa…
416 { ARM::VST1q8LowQPseudo_UPD, ARM::VST1d8Qwb_fixed, false, true, true, SingleLowSpc, 4, 8 ,fals…
417 { ARM::VST1q8LowTPseudo_UPD, ARM::VST1d8Twb_fixed, false, true, true, SingleLowSpc, 3, 8 ,fals…
419 { ARM::VST2LNd16Pseudo, ARM::VST2LNd16, false, false, false, SingleSpc, 2, 4 ,true},
420 { ARM::VST2LNd16Pseudo_UPD, ARM::VST2LNd16_UPD, false, true, true, SingleSpc, 2, 4 ,true},
421 { ARM::VST2LNd32Pseudo, ARM::VST2LNd32, false, false, false, SingleSpc, 2, 2 ,true},
422 { ARM::VST2LNd32Pseudo_UPD, ARM::VST2LNd32_UPD, false, true, true, SingleSpc, 2, 2 ,true},
423 { ARM::VST2LNd8Pseudo, ARM::VST2LNd8, false, false, false, SingleSpc, 2, 8 ,true},
424 { ARM::VST2LNd8Pseudo_UPD, ARM::VST2LNd8_UPD, false, true, true, SingleSpc, 2, 8 ,true},
425 { ARM::VST2LNq16Pseudo, ARM::VST2LNq16, false, false, false, EvenDblSpc, 2, 4,true},
426 { ARM::VST2LNq16Pseudo_UPD, ARM::VST2LNq16_UPD, false, true, true, EvenDblSpc, 2, 4,true},
427 { ARM::VST2LNq32Pseudo, ARM::VST2LNq32, false, false, false, EvenDblSpc, 2, 2,true},
428 { ARM::VST2LNq32Pseudo_UPD, ARM::VST2LNq32_UPD, false, true, true, EvenDblSpc, 2, 2,true},
430 { ARM::VST2q16Pseudo, ARM::VST2q16, false, false, false, SingleSpc, 4, 4 ,false},
431 { ARM::VST2q16PseudoWB_fixed, ARM::VST2q16wb_fixed, false, true, false, SingleSpc, 4, 4 ,false},
432 { ARM::VST2q16PseudoWB_register, ARM::VST2q16wb_register, false, true, true, SingleSpc, 4, 4 ,f…
433 { ARM::VST2q32Pseudo, ARM::VST2q32, false, false, false, SingleSpc, 4, 2 ,false},
434 { ARM::VST2q32PseudoWB_fixed, ARM::VST2q32wb_fixed, false, true, false, SingleSpc, 4, 2 ,false},
435 { ARM::VST2q32PseudoWB_register, ARM::VST2q32wb_register, false, true, true, SingleSpc, 4, 2 ,f…
436 { ARM::VST2q8Pseudo, ARM::VST2q8, false, false, false, SingleSpc, 4, 8 ,false},
437 { ARM::VST2q8PseudoWB_fixed, ARM::VST2q8wb_fixed, false, true, false, SingleSpc, 4, 8 ,false},
438 { ARM::VST2q8PseudoWB_register, ARM::VST2q8wb_register, false, true, true, SingleSpc, 4, 8 ,fa…
440 { ARM::VST3LNd16Pseudo, ARM::VST3LNd16, false, false, false, SingleSpc, 3, 4 ,true},
441 { ARM::VST3LNd16Pseudo_UPD, ARM::VST3LNd16_UPD, false, true, true, SingleSpc, 3, 4 ,true},
442 { ARM::VST3LNd32Pseudo, ARM::VST3LNd32, false, false, false, SingleSpc, 3, 2 ,true},
443 { ARM::VST3LNd32Pseudo_UPD, ARM::VST3LNd32_UPD, false, true, true, SingleSpc, 3, 2 ,true},
444 { ARM::VST3LNd8Pseudo, ARM::VST3LNd8, false, false, false, SingleSpc, 3, 8 ,true},
445 { ARM::VST3LNd8Pseudo_UPD, ARM::VST3LNd8_UPD, false, true, true, SingleSpc, 3, 8 ,true},
446 { ARM::VST3LNq16Pseudo, ARM::VST3LNq16, false, false, false, EvenDblSpc, 3, 4,true},
447 { ARM::VST3LNq16Pseudo_UPD, ARM::VST3LNq16_UPD, false, true, true, EvenDblSpc, 3, 4,true},
448 { ARM::VST3LNq32Pseudo, ARM::VST3LNq32, false, false, false, EvenDblSpc, 3, 2,true},
449 { ARM::VST3LNq32Pseudo_UPD, ARM::VST3LNq32_UPD, false, true, true, EvenDblSpc, 3, 2,true},
451 { ARM::VST3d16Pseudo, ARM::VST3d16, false, false, false, SingleSpc, 3, 4 ,true},
452 { ARM::VST3d16Pseudo_UPD, ARM::VST3d16_UPD, false, true, true, SingleSpc, 3, 4 ,true},
453 { ARM::VST3d32Pseudo, ARM::VST3d32, false, false, false, SingleSpc, 3, 2 ,true},
454 { ARM::VST3d32Pseudo_UPD, ARM::VST3d32_UPD, false, true, true, SingleSpc, 3, 2 ,true},
455 { ARM::VST3d8Pseudo, ARM::VST3d8, false, false, false, SingleSpc, 3, 8 ,true},
456 { ARM::VST3d8Pseudo_UPD, ARM::VST3d8_UPD, false, true, true, SingleSpc, 3, 8 ,true},
458 { ARM::VST3q16Pseudo_UPD, ARM::VST3q16_UPD, false, true, true, EvenDblSpc, 3, 4 ,true},
459 { ARM::VST3q16oddPseudo, ARM::VST3q16, false, false, false, OddDblSpc, 3, 4 ,true},
460 { ARM::VST3q16oddPseudo_UPD, ARM::VST3q16_UPD, false, true, true, OddDblSpc, 3, 4 ,true},
461 { ARM::VST3q32Pseudo_UPD, ARM::VST3q32_UPD, false, true, true, EvenDblSpc, 3, 2 ,true},
462 { ARM::VST3q32oddPseudo, ARM::VST3q32, false, false, false, OddDblSpc, 3, 2 ,true},
463 { ARM::VST3q32oddPseudo_UPD, ARM::VST3q32_UPD, false, true, true, OddDblSpc, 3, 2 ,true},
464 { ARM::VST3q8Pseudo_UPD, ARM::VST3q8_UPD, false, true, true, EvenDblSpc, 3, 8 ,true},
465 { ARM::VST3q8oddPseudo, ARM::VST3q8, false, false, false, OddDblSpc, 3, 8 ,true},
466 { ARM::VST3q8oddPseudo_UPD, ARM::VST3q8_UPD, false, true, true, OddDblSpc, 3, 8 ,true},
468 { ARM::VST4LNd16Pseudo, ARM::VST4LNd16, false, false, false, SingleSpc, 4, 4 ,true},
469 { ARM::VST4LNd16Pseudo_UPD, ARM::VST4LNd16_UPD, false, true, true, SingleSpc, 4, 4 ,true},
470 { ARM::VST4LNd32Pseudo, ARM::VST4LNd32, false, false, false, SingleSpc, 4, 2 ,true},
471 { ARM::VST4LNd32Pseudo_UPD, ARM::VST4LNd32_UPD, false, true, true, SingleSpc, 4, 2 ,true},
472 { ARM::VST4LNd8Pseudo, ARM::VST4LNd8, false, false, false, SingleSpc, 4, 8 ,true},
473 { ARM::VST4LNd8Pseudo_UPD, ARM::VST4LNd8_UPD, false, true, true, SingleSpc, 4, 8 ,true},
474 { ARM::VST4LNq16Pseudo, ARM::VST4LNq16, false, false, false, EvenDblSpc, 4, 4,true},
475 { ARM::VST4LNq16Pseudo_UPD, ARM::VST4LNq16_UPD, false, true, true, EvenDblSpc, 4, 4,true},
476 { ARM::VST4LNq32Pseudo, ARM::VST4LNq32, false, false, false, EvenDblSpc, 4, 2,true},
477 { ARM::VST4LNq32Pseudo_UPD, ARM::VST4LNq32_UPD, false, true, true, EvenDblSpc, 4, 2,true},
479 { ARM::VST4d16Pseudo, ARM::VST4d16, false, false, false, SingleSpc, 4, 4 ,true},
480 { ARM::VST4d16Pseudo_UPD, ARM::VST4d16_UPD, false, true, true, SingleSpc, 4, 4 ,true},
481 { ARM::VST4d32Pseudo, ARM::VST4d32, false, false, false, SingleSpc, 4, 2 ,true},
482 { ARM::VST4d32Pseudo_UPD, ARM::VST4d32_UPD, false, true, true, SingleSpc, 4, 2 ,true},
483 { ARM::VST4d8Pseudo, ARM::VST4d8, false, false, false, SingleSpc, 4, 8 ,true},
484 { ARM::VST4d8Pseudo_UPD, ARM::VST4d8_UPD, false, true, true, SingleSpc, 4, 8 ,true},
486 { ARM::VST4q16Pseudo_UPD, ARM::VST4q16_UPD, false, true, true, EvenDblSpc, 4, 4 ,true},
487 { ARM::VST4q16oddPseudo, ARM::VST4q16, false, false, false, OddDblSpc, 4, 4 ,true},
488 { ARM::VST4q16oddPseudo_UPD, ARM::VST4q16_UPD, false, true, true, OddDblSpc, 4, 4 ,true},
489 { ARM::VST4q32Pseudo_UPD, ARM::VST4q32_UPD, false, true, true, EvenDblSpc, 4, 2 ,true},
490 { ARM::VST4q32oddPseudo, ARM::VST4q32, false, false, false, OddDblSpc, 4, 2 ,true},
491 { ARM::VST4q32oddPseudo_UPD, ARM::VST4q32_UPD, false, true, true, OddDblSpc, 4, 2 ,true},
492 { ARM::VST4q8Pseudo_UPD, ARM::VST4q8_UPD, false, true, true, EvenDblSpc, 4, 8 ,true},
493 { ARM::VST4q8oddPseudo, ARM::VST4q8, false, false, false, OddDblSpc, 4, 8 ,true},
494 { ARM::VST4q8oddPseudo_UPD, ARM::VST4q8_UPD, false, true, true, OddDblSpc, 4, 8 ,true}
522 D0 = TRI->getSubReg(Reg, ARM::dsub_0); in GetDSubRegs()
523 D1 = TRI->getSubReg(Reg, ARM::dsub_1); in GetDSubRegs()
524 D2 = TRI->getSubReg(Reg, ARM::dsub_2); in GetDSubRegs()
525 D3 = TRI->getSubReg(Reg, ARM::dsub_3); in GetDSubRegs()
527 D0 = TRI->getSubReg(Reg, ARM::dsub_4); in GetDSubRegs()
528 D1 = TRI->getSubReg(Reg, ARM::dsub_5); in GetDSubRegs()
529 D2 = TRI->getSubReg(Reg, ARM::dsub_6); in GetDSubRegs()
530 D3 = TRI->getSubReg(Reg, ARM::dsub_7); in GetDSubRegs()
532 D0 = TRI->getSubReg(Reg, ARM::dsub_3); in GetDSubRegs()
533 D1 = TRI->getSubReg(Reg, ARM::dsub_4); in GetDSubRegs()
534 D2 = TRI->getSubReg(Reg, ARM::dsub_5); in GetDSubRegs()
535 D3 = TRI->getSubReg(Reg, ARM::dsub_6); in GetDSubRegs()
537 D0 = TRI->getSubReg(Reg, ARM::dsub_0); in GetDSubRegs()
538 D1 = TRI->getSubReg(Reg, ARM::dsub_2); in GetDSubRegs()
539 D2 = TRI->getSubReg(Reg, ARM::dsub_4); in GetDSubRegs()
540 D3 = TRI->getSubReg(Reg, ARM::dsub_6); in GetDSubRegs()
543 D0 = TRI->getSubReg(Reg, ARM::dsub_1); in GetDSubRegs()
544 D1 = TRI->getSubReg(Reg, ARM::dsub_3); in GetDSubRegs()
545 D2 = TRI->getSubReg(Reg, ARM::dsub_5); in GetDSubRegs()
546 D3 = TRI->getSubReg(Reg, ARM::dsub_7); in GetDSubRegs()
569 bool IsVLD2DUP = TableEntry->RealOpc == ARM::VLD2DUPd8x2 || in ExpandVLD()
570 TableEntry->RealOpc == ARM::VLD2DUPd16x2 || in ExpandVLD()
571 TableEntry->RealOpc == ARM::VLD2DUPd32x2 || in ExpandVLD()
572 TableEntry->RealOpc == ARM::VLD2DUPd8x2wb_fixed || in ExpandVLD()
573 TableEntry->RealOpc == ARM::VLD2DUPd16x2wb_fixed || in ExpandVLD()
574 TableEntry->RealOpc == ARM::VLD2DUPd32x2wb_fixed || in ExpandVLD()
575 TableEntry->RealOpc == ARM::VLD2DUPd8x2wb_register || in ExpandVLD()
576 TableEntry->RealOpc == ARM::VLD2DUPd16x2wb_register || in ExpandVLD()
577 TableEntry->RealOpc == ARM::VLD2DUPd32x2wb_register; in ExpandVLD()
582 SubRegIndex = ARM::dsub_0; in ExpandVLD()
585 SubRegIndex = ARM::dsub_1; in ExpandVLD()
588 unsigned DstRegPair = TRI->getMatchingSuperReg(SubReg, ARM::dsub_0, in ExpandVLD()
589 &ARM::DPairSpcRegClass); in ExpandVLD()
620 if (TableEntry->RealOpc == ARM::VLD1d8Qwb_fixed || in ExpandVLD()
621 TableEntry->RealOpc == ARM::VLD1d16Qwb_fixed || in ExpandVLD()
622 TableEntry->RealOpc == ARM::VLD1d32Qwb_fixed || in ExpandVLD()
623 TableEntry->RealOpc == ARM::VLD1d64Qwb_fixed || in ExpandVLD()
624 TableEntry->RealOpc == ARM::VLD1d8Twb_fixed || in ExpandVLD()
625 TableEntry->RealOpc == ARM::VLD1d16Twb_fixed || in ExpandVLD()
626 TableEntry->RealOpc == ARM::VLD1d32Twb_fixed || in ExpandVLD()
627 TableEntry->RealOpc == ARM::VLD1d64Twb_fixed || in ExpandVLD()
628 TableEntry->RealOpc == ARM::VLD2DUPd8x2wb_fixed || in ExpandVLD()
629 TableEntry->RealOpc == ARM::VLD2DUPd16x2wb_fixed || in ExpandVLD()
630 TableEntry->RealOpc == ARM::VLD2DUPd32x2wb_fixed) { in ExpandVLD()
699 if (TableEntry->RealOpc == ARM::VST1d8Qwb_fixed || in ExpandVST()
700 TableEntry->RealOpc == ARM::VST1d16Qwb_fixed || in ExpandVST()
701 TableEntry->RealOpc == ARM::VST1d32Qwb_fixed || in ExpandVST()
702 TableEntry->RealOpc == ARM::VST1d64Qwb_fixed || in ExpandVST()
703 TableEntry->RealOpc == ARM::VST1d8Twb_fixed || in ExpandVST()
704 TableEntry->RealOpc == ARM::VST1d16Twb_fixed || in ExpandVST()
705 TableEntry->RealOpc == ARM::VST1d32Twb_fixed || in ExpandVST()
706 TableEntry->RealOpc == ARM::VST1d64Twb_fixed) { in ExpandVST()
877 MI.getOpcode() == ARM::MQQPRStore || MI.getOpcode() == ARM::MQQQQPRStore in ExpandMQQPRLoadStore()
878 ? ARM::VSTMDIA in ExpandMQQPRLoadStore()
879 : ARM::VLDMDIA; in ExpandMQQPRLoadStore()
890 MIB.addReg(TRI->getSubReg(SrcReg, ARM::dsub_0), Flags); in ExpandMQQPRLoadStore()
891 MIB.addReg(TRI->getSubReg(SrcReg, ARM::dsub_1), Flags); in ExpandMQQPRLoadStore()
892 MIB.addReg(TRI->getSubReg(SrcReg, ARM::dsub_2), Flags); in ExpandMQQPRLoadStore()
893 MIB.addReg(TRI->getSubReg(SrcReg, ARM::dsub_3), Flags); in ExpandMQQPRLoadStore()
894 if (MI.getOpcode() == ARM::MQQQQPRStore || in ExpandMQQPRLoadStore()
895 MI.getOpcode() == ARM::MQQQQPRLoad) { in ExpandMQQPRLoadStore()
896 MIB.addReg(TRI->getSubReg(SrcReg, ARM::dsub_4), Flags); in ExpandMQQPRLoadStore()
897 MIB.addReg(TRI->getSubReg(SrcReg, ARM::dsub_5), Flags); in ExpandMQQPRLoadStore()
898 MIB.addReg(TRI->getSubReg(SrcReg, ARM::dsub_6), Flags); in ExpandMQQPRLoadStore()
899 MIB.addReg(TRI->getSubReg(SrcReg, ARM::dsub_7), Flags); in ExpandMQQPRLoadStore()
902 if (NewOpc == ARM::VSTMDIA) in ExpandMQQPRLoadStore()
1016 unsigned Op = PendingShift ? ARM::tADDi8 : ARM::tMOVi8; in ExpandTMOV32BitImm()
1022 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::tLSLri), DstReg) in ExpandTMOV32BitImm()
1038 if (Op == ARM::tADDi8) in ExpandTMOV32BitImm()
1043 LLVM_DEBUG(dbgs() << (Op == ARM::tMOVi8 ? "To: " : "And:") << " "; in ExpandTMOV32BitImm()
1067 bool isCC = Opcode == ARM::MOVCCi32imm || Opcode == ARM::t2MOVCCi32imm; in ExpandMOV32BitImm()
1074 (Opcode == ARM::MOVi32imm || Opcode == ARM::MOVCCi32imm)) { in ExpandMOV32BitImm()
1075 // FIXME Windows CE supports older ARM CPUs in ExpandMOV32BitImm()
1076 assert(!STI->isTargetWindows() && "Windows on ARM requires ARMv7+"); in ExpandMOV32BitImm()
1083 LO16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVi), DstReg); in ExpandMOV32BitImm()
1084 HI16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::ORRri)) in ExpandMOV32BitImm()
1090 LO16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MVNi), DstReg); in ExpandMOV32BitImm()
1091 HI16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::SUBri)) in ExpandMOV32BitImm()
1119 if (Opcode == ARM::t2MOVi32imm || Opcode == ARM::t2MOVCCi32imm) { in ExpandMOV32BitImm()
1120 LO16Opc = ARM::t2MOVi16; in ExpandMOV32BitImm()
1121 HI16Opc = ARM::t2MOVTi16; in ExpandMOV32BitImm()
1123 LO16Opc = ARM::MOVi16; in ExpandMOV32BitImm()
1124 HI16Opc = ARM::MOVTi16; in ExpandMOV32BitImm()
1185 BuildMI(MBB, MBBI, DL, TII->get(ARM::t2CLRM)).add(predOps(ARMCC::AL)); in CMSEClearGPRegs()
1188 CLRM.addReg(ARM::APSR, RegState::Define); in CMSEClearGPRegs()
1189 CLRM.addReg(ARM::CPSR, RegState::Define | RegState::Implicit); in CMSEClearGPRegs()
1196 BuildMI(MBB, MBBI, DL, TII->get(ARM::tMOVr), Reg) in CMSEClearGPRegs()
1201 BuildMI(MBB, MBBI, DL, TII->get(ARM::t2MSR_M)) in CMSEClearGPRegs()
1221 if ((Reg >= ARM::Q0 && Reg <= ARM::Q7) || in determineFPRegsToClear()
1222 (Reg >= ARM::D0 && Reg <= ARM::D15) || in determineFPRegsToClear()
1223 (Reg >= ARM::S0 && Reg <= ARM::S31)) in determineFPRegsToClear()
1228 if (Reg >= ARM::Q0 && Reg <= ARM::Q7) { in determineFPRegsToClear()
1229 int R = Reg - ARM::Q0; in determineFPRegsToClear()
1231 } else if (Reg >= ARM::D0 && Reg <= ARM::D15) { in determineFPRegsToClear()
1232 int R = Reg - ARM::D0; in determineFPRegsToClear()
1234 } else if (Reg >= ARM::S0 && Reg <= ARM::S31) { in determineFPRegsToClear()
1235 ClearRegs[Reg - ARM::S0] = false; in determineFPRegsToClear()
1291 if (Reg == ARM::NoRegister || Reg == ARM::LR) in CMSEClearFPRegsV8()
1297 ClearBB->addLiveIn(ARM::LR); in CMSEClearFPRegsV8()
1298 DoneBB->addLiveIn(ARM::LR); in CMSEClearFPRegsV8()
1301 BuildMI(MBB, MBB.end(), DL, TII->get(ARM::t2MRS_M), ARM::R12) in CMSEClearFPRegsV8()
1305 BuildMI(MBB, MBB.end(), DL, TII->get(ARM::t2TSTri)) in CMSEClearFPRegsV8()
1306 .addReg(ARM::R12) in CMSEClearFPRegsV8()
1310 BuildMI(MBB, MBB.end(), DL, TII->get(ARM::tBcc)) in CMSEClearFPRegsV8()
1313 .addReg(ARM::CPSR, RegState::Kill); in CMSEClearFPRegsV8()
1320 unsigned Reg = ARM::D0 + D; in CMSEClearFPRegsV8()
1321 BuildMI(ClearBB, DL, TII->get(ARM::VMOVDRR), Reg) in CMSEClearFPRegsV8()
1322 .addReg(ARM::LR) in CMSEClearFPRegsV8()
1323 .addReg(ARM::LR) in CMSEClearFPRegsV8()
1328 unsigned Reg = ARM::S0 + D * 2; in CMSEClearFPRegsV8()
1329 BuildMI(ClearBB, DL, TII->get(ARM::VMOVSR), Reg) in CMSEClearFPRegsV8()
1330 .addReg(ARM::LR) in CMSEClearFPRegsV8()
1335 unsigned Reg = ARM::S0 + D * 2 + 1; in CMSEClearFPRegsV8()
1336 BuildMI(ClearBB, DL, TII->get(ARM::VMOVSR), Reg) in CMSEClearFPRegsV8()
1337 .addReg(ARM::LR) in CMSEClearFPRegsV8()
1345 BuildMI(ClearBB, DL, TII->get(ARM::VMRS), ARM::R12) in CMSEClearFPRegsV8()
1347 BuildMI(ClearBB, DL, TII->get(ARM::t2BICri), ARM::R12) in CMSEClearFPRegsV8()
1348 .addReg(ARM::R12) in CMSEClearFPRegsV8()
1352 BuildMI(ClearBB, DL, TII->get(ARM::t2BICri), ARM::R12) in CMSEClearFPRegsV8()
1353 .addReg(ARM::R12) in CMSEClearFPRegsV8()
1357 BuildMI(ClearBB, DL, TII->get(ARM::VMSR)) in CMSEClearFPRegsV8()
1358 .addReg(ARM::R12) in CMSEClearFPRegsV8()
1381 BuildMI(MBB, MBBI, RetI.getDebugLoc(), TII->get(ARM::VSCCLRMS)) in CMSEClearFPRegsV81()
1384 VSCCLRM.addReg(ARM::S0 + Start, RegState::Define); in CMSEClearFPRegsV81()
1385 VSCCLRM.addReg(ARM::VPR, RegState::Define); in CMSEClearFPRegsV81()
1392 BuildMI(MBB, MBBI, RetI.getDebugLoc(), TII->get(ARM::VSCCLRMS)) in CMSEClearFPRegsV81()
1395 VSCCLRM.addReg(ARM::S0 + Start, RegState::Define); in CMSEClearFPRegsV81()
1396 VSCCLRM.addReg(ARM::VPR, RegState::Define); in CMSEClearFPRegsV81()
1421 BuildMI(MBB, MBBI, DL, TII->get(ARM::tSUBspi), ARM::SP) in CMSESaveClearFPRegsV8()
1422 .addReg(ARM::SP) in CMSESaveClearFPRegsV8()
1432 assert(!ARM::DPRRegClass.contains(Reg) || in CMSESaveClearFPRegsV8()
1433 ARM::DPR_VFP2RegClass.contains(Reg)); in CMSESaveClearFPRegsV8()
1434 assert(!ARM::QPRRegClass.contains(Reg)); in CMSESaveClearFPRegsV8()
1435 if (ARM::DPR_VFP2RegClass.contains(Reg)) { in CMSESaveClearFPRegsV8()
1442 BuildMI(MBB, MBBI, DL, TII->get(ARM::VMOVRRD)) in CMSESaveClearFPRegsV8()
1450 } else if (ARM::SPRRegClass.contains(Reg)) { in CMSESaveClearFPRegsV8()
1456 BuildMI(MBB, MBBI, DL, TII->get(ARM::VMOVRS), SaveReg) in CMSESaveClearFPRegsV8()
1474 BuildMI(MBB, MBBI, DL, TII->get(ARM::VLSTM)) in CMSESaveClearFPRegsV8()
1475 .addReg(ARM::SP) in CMSESaveClearFPRegsV8()
1491 if (ARM::DPR_VFP2RegClass.contains(Reg)) in CMSESaveClearFPRegsV8()
1492 BuildMI(MBB, MBBI, DL, TII->get(ARM::VMOVDRR), Reg) in CMSESaveClearFPRegsV8()
1496 else if (ARM::SPRRegClass.contains(Reg)) in CMSESaveClearFPRegsV8()
1497 BuildMI(MBB, MBBI, DL, TII->get(ARM::VMOVSR), Reg) in CMSESaveClearFPRegsV8()
1503 if (ARM::DPR_VFP2RegClass.contains(Reg)) { in CMSESaveClearFPRegsV8()
1505 BuildMI(MBB, MBBI, DL, TII->get(ARM::VLDRD), Reg) in CMSESaveClearFPRegsV8()
1506 .addReg(ARM::SP) in CMSESaveClearFPRegsV8()
1507 .addImm((Reg - ARM::D0) * 2) in CMSESaveClearFPRegsV8()
1512 unsigned SReg0 = TRI->getSubReg(Reg, ARM::ssub_0); in CMSESaveClearFPRegsV8()
1513 BuildMI(MBB, MBBI, DL, TII->get(ARM::VLDRS), SReg0) in CMSESaveClearFPRegsV8()
1514 .addReg(ARM::SP) in CMSESaveClearFPRegsV8()
1515 .addImm((Reg - ARM::D0) * 2) in CMSESaveClearFPRegsV8()
1517 BuildMI(MBB, MBBI, DL, TII->get(ARM::VLDRS), SReg0 + 1) in CMSESaveClearFPRegsV8()
1518 .addReg(ARM::SP) in CMSESaveClearFPRegsV8()
1519 .addImm((Reg - ARM::D0) * 2 + 1) in CMSESaveClearFPRegsV8()
1522 } else if (ARM::SPRRegClass.contains(Reg)) { in CMSESaveClearFPRegsV8()
1523 BuildMI(MBB, MBBI, DL, TII->get(ARM::VLDRS), Reg) in CMSESaveClearFPRegsV8()
1524 .addReg(ARM::SP) in CMSESaveClearFPRegsV8()
1525 .addImm(Reg - ARM::S0) in CMSESaveClearFPRegsV8()
1532 BuildMI(MBB, MBBI, DL, TII->get(ARM::tLDRspi), SpareReg) in CMSESaveClearFPRegsV8()
1533 .addReg(ARM::SP) in CMSESaveClearFPRegsV8()
1536 BuildMI(MBB, MBBI, DL, TII->get(ARM::t2BICri), SpareReg) in CMSESaveClearFPRegsV8()
1541 BuildMI(MBB, MBBI, DL, TII->get(ARM::t2BICri), SpareReg) in CMSESaveClearFPRegsV8()
1546 BuildMI(MBB, MBBI, DL, TII->get(ARM::VMSR)) in CMSESaveClearFPRegsV8()
1567 BuildMI(MBB, MBBI, DL, TII->get(ARM::tSUBspi), ARM::SP) in CMSESaveClearFPRegsV81()
1568 .addReg(ARM::SP) in CMSESaveClearFPRegsV81()
1574 BuildMI(MBB, MBBI, DL, TII->get(ARM::VLSTM)) in CMSESaveClearFPRegsV81()
1575 .addReg(ARM::SP) in CMSESaveClearFPRegsV81()
1589 BuildMI(MBB, MBBI, DL, TII->get(ARM::VSTMSDB_UPD), ARM::SP) in CMSESaveClearFPRegsV81()
1590 .addReg(ARM::SP) in CMSESaveClearFPRegsV81()
1592 for (int Reg = ARM::S16; Reg <= ARM::S31; ++Reg) in CMSESaveClearFPRegsV81()
1599 BuildMI(MBB, MBBI, DL, TII->get(ARM::VSTR_FPCXTS_pre), ARM::SP) in CMSESaveClearFPRegsV81()
1600 .addReg(ARM::SP) in CMSESaveClearFPRegsV81()
1621 unsigned ScratchReg = ARM::NoRegister; in CMSERestoreFPRegsV8()
1631 assert(!ARM::DPRRegClass.contains(Reg) || in CMSERestoreFPRegsV8()
1632 ARM::DPR_VFP2RegClass.contains(Reg)); in CMSERestoreFPRegsV8()
1633 assert(!ARM::QPRRegClass.contains(Reg)); in CMSERestoreFPRegsV8()
1634 if (ARM::DPR_VFP2RegClass.contains(Reg)) { in CMSERestoreFPRegsV8()
1641 BuildMI(MBB, MBBI, DL, TII->get(ARM::VMOVRRD)) in CMSERestoreFPRegsV8()
1649 } else if (ARM::SPRRegClass.contains(Reg)) { in CMSERestoreFPRegsV8()
1655 BuildMI(MBB, MBBI, DL, TII->get(ARM::VMOVRS), SaveReg) in CMSERestoreFPRegsV8()
1672 if (ARM::DPR_VFP2RegClass.contains(Reg)) in CMSERestoreFPRegsV8()
1673 BuildMI(MBB, MBBI, DL, TII->get(ARM::VSTRD)) in CMSERestoreFPRegsV8()
1675 .addReg(ARM::SP) in CMSERestoreFPRegsV8()
1676 .addImm((Reg - ARM::D0) * 2) in CMSERestoreFPRegsV8()
1678 else if (ARM::SPRRegClass.contains(Reg)) in CMSERestoreFPRegsV8()
1679 BuildMI(MBB, MBBI, DL, TII->get(ARM::VSTRS)) in CMSERestoreFPRegsV8()
1681 .addReg(ARM::SP) in CMSERestoreFPRegsV8()
1682 .addImm(Reg - ARM::S0) in CMSERestoreFPRegsV8()
1689 BuildMI(MBB, MBBI, DL, TII->get(ARM::VLLDM)) in CMSERestoreFPRegsV8()
1690 .addReg(ARM::SP) in CMSERestoreFPRegsV8()
1698 Bundler.append(BuildMI(*MBB.getParent(), DL, TII->get(ARM::t2MRS_M)) in CMSERestoreFPRegsV8()
1703 Bundler.append(BuildMI(*MBB.getParent(), DL, TII->get(ARM::t2TSTri)) in CMSERestoreFPRegsV8()
1708 Bundler.append(BuildMI(*MBB.getParent(), DL, TII->get(ARM::t2IT)) in CMSERestoreFPRegsV8()
1716 Bundler.append(BuildMI(*MBB.getParent(), DL, TII->get(ARM::VMOVS)) in CMSERestoreFPRegsV8()
1717 .addReg(ARM::S0, RegState::Define) in CMSERestoreFPRegsV8()
1718 .addReg(ARM::S0, RegState::Undef) in CMSERestoreFPRegsV8()
1721 Bundler.append(BuildMI(*MBB.getParent(), DL, TII->get(ARM::INLINEASM)) in CMSERestoreFPRegsV8()
1731 if (ARM::DPR_VFP2RegClass.contains(Reg)) in CMSERestoreFPRegsV8()
1732 BuildMI(MBB, MBBI, DL, TII->get(ARM::VMOVDRR), Reg) in CMSERestoreFPRegsV8()
1736 else if (ARM::SPRRegClass.contains(Reg)) in CMSERestoreFPRegsV8()
1737 BuildMI(MBB, MBBI, DL, TII->get(ARM::VMOVSR), Reg) in CMSERestoreFPRegsV8()
1743 BuildMI(MBB, MBBI, DL, TII->get(ARM::tADDspi), ARM::SP) in CMSERestoreFPRegsV8()
1744 .addReg(ARM::SP) in CMSERestoreFPRegsV8()
1754 if ((Reg >= ARM::Q0 && Reg <= ARM::Q7) || in definesOrUsesFPReg()
1755 (Reg >= ARM::D0 && Reg <= ARM::D15) || in definesOrUsesFPReg()
1756 (Reg >= ARM::S0 && Reg <= ARM::S31)) in definesOrUsesFPReg()
1767 BuildMI(MBB, MBBI, DL, TII->get(ARM::VSCCLRMS)) in CMSERestoreFPRegsV81()
1769 .addReg(ARM::VPR, RegState::Define); in CMSERestoreFPRegsV81()
1773 BuildMI(MBB, MBBI, DL, TII->get(ARM::VLLDM)) in CMSERestoreFPRegsV81()
1774 .addReg(ARM::SP) in CMSERestoreFPRegsV81()
1780 BuildMI(MBB, MBBI, DL, TII->get(ARM::tADDspi), ARM::SP) in CMSERestoreFPRegsV81()
1781 .addReg(ARM::SP) in CMSERestoreFPRegsV81()
1786 BuildMI(MBB, MBBI, MBBI->getDebugLoc(), TII->get(ARM::VLDR_FPCXTS_post), in CMSERestoreFPRegsV81()
1787 ARM::SP) in CMSERestoreFPRegsV81()
1788 .addReg(ARM::SP) in CMSERestoreFPRegsV81()
1794 BuildMI(MBB, MBBI, DL, TII->get(ARM::VLDMSIA_UPD), ARM::SP) in CMSERestoreFPRegsV81()
1795 .addReg(ARM::SP) in CMSERestoreFPRegsV81()
1797 for (int Reg = ARM::S16; Reg <= ARM::S31; ++Reg) in CMSERestoreFPRegsV81()
1826 assert((UxtOp == 0 || UxtOp == ARM::tUXTB || UxtOp == ARM::tUXTH) && in ExpandCMP_SWAP()
1828 assert((UxtOp == 0 || ARM::tGPRRegClass.contains(DesiredReg)) && in ExpandCMP_SWAP()
1858 if (LdrexOp == ARM::t2LDREX) in ExpandCMP_SWAP()
1862 unsigned CMPrr = IsThumb ? ARM::tCMPhir : ARM::CMPrr; in ExpandCMP_SWAP()
1867 unsigned Bcc = IsThumb ? ARM::tBcc : ARM::Bcc; in ExpandCMP_SWAP()
1871 .addReg(ARM::CPSR, RegState::Kill); in ExpandCMP_SWAP()
1882 if (StrexOp == ARM::t2STREX) in ExpandCMP_SWAP()
1887 IsThumb ? (IsThumb1Only ? ARM::tCMPi8 : ARM::t2CMPri) : ARM::CMPri; in ExpandCMP_SWAP()
1895 .addReg(ARM::CPSR, RegState::Kill); in ExpandCMP_SWAP()
1921 /// ARM's ldrexd/strexd take a consecutive register pair (represented as a
1928 Register RegLo = TRI->getSubReg(Reg.getReg(), ARM::gsub_0); in addExclusiveRegPair()
1929 Register RegHi = TRI->getSubReg(Reg.getReg(), ARM::gsub_1); in addExclusiveRegPair()
1954 Register DestLo = TRI->getSubReg(Dest.getReg(), ARM::gsub_0); in ExpandCMP_SWAP_64()
1955 Register DestHi = TRI->getSubReg(Dest.getReg(), ARM::gsub_1); in ExpandCMP_SWAP_64()
1956 Register DesiredLo = TRI->getSubReg(DesiredReg, ARM::gsub_0); in ExpandCMP_SWAP_64()
1957 Register DesiredHi = TRI->getSubReg(DesiredReg, ARM::gsub_1); in ExpandCMP_SWAP_64()
1973 unsigned LDREXD = IsThumb ? ARM::t2LDREXD : ARM::LDREXD; in ExpandCMP_SWAP_64()
1979 unsigned CMPrr = IsThumb ? ARM::tCMPhir : ARM::CMPrr; in ExpandCMP_SWAP_64()
1988 .addImm(ARMCC::EQ).addReg(ARM::CPSR, RegState::Kill); in ExpandCMP_SWAP_64()
1990 unsigned Bcc = IsThumb ? ARM::tBcc : ARM::Bcc; in ExpandCMP_SWAP_64()
1994 .addReg(ARM::CPSR, RegState::Kill); in ExpandCMP_SWAP_64()
2002 unsigned STREXD = IsThumb ? ARM::t2STREXD : ARM::STREXD; in ExpandCMP_SWAP_64()
2008 unsigned CMPri = IsThumb ? ARM::t2CMPri : ARM::CMPri; in ExpandCMP_SWAP_64()
2016 .addReg(ARM::CPSR, RegState::Kill); in ExpandCMP_SWAP_64()
2049 BuildMI(MBB, MBBI, DL, TII.get(ARM::tPUSH)).add(predOps(ARMCC::AL)); in CMSEPushCalleeSaves()
2050 for (int Reg = ARM::R4; Reg < ARM::R8; ++Reg) { in CMSEPushCalleeSaves()
2062 for (int LoReg = ARM::R7, HiReg = ARM::R11; LoReg >= ARM::R4; --LoReg) { in CMSEPushCalleeSaves()
2065 BuildMI(MBB, MBBI, DL, TII.get(ARM::tMOVr), LoReg) in CMSEPushCalleeSaves()
2071 BuildMI(MBB, MBBI, DL, TII.get(ARM::tPUSH)).add(predOps(ARMCC::AL)); in CMSEPushCalleeSaves()
2072 for (int Reg = ARM::R4; Reg < ARM::R8; ++Reg) { in CMSEPushCalleeSaves()
2081 if (JumpReg >= ARM::R4 && JumpReg <= ARM::R7) { in CMSEPushCalleeSaves()
2082 int LoReg = JumpReg == ARM::R4 ? ARM::R5 : ARM::R4; in CMSEPushCalleeSaves()
2083 BuildMI(MBB, MBBI, DL, TII.get(ARM::tMOVr), LoReg) in CMSEPushCalleeSaves()
2084 .addReg(ARM::R8, LiveRegs.contains(ARM::R8) ? 0 : RegState::Undef) in CMSEPushCalleeSaves()
2086 BuildMI(MBB, MBBI, DL, TII.get(ARM::tPUSH)) in CMSEPushCalleeSaves()
2092 BuildMI(MBB, MBBI, DL, TII.get(ARM::t2STMDB_UPD), ARM::SP) in CMSEPushCalleeSaves()
2093 .addReg(ARM::SP) in CMSEPushCalleeSaves()
2095 for (int Reg = ARM::R4; Reg < ARM::R12; ++Reg) { in CMSEPushCalleeSaves()
2109 BuildMI(MBB, MBBI, DL, TII.get(ARM::tPOP)).add(predOps(ARMCC::AL)); in CMSEPopCalleeSaves()
2111 PopMIB.addReg(ARM::R4 + R, RegState::Define); in CMSEPopCalleeSaves()
2112 BuildMI(MBB, MBBI, DL, TII.get(ARM::tMOVr), ARM::R8 + R) in CMSEPopCalleeSaves()
2113 .addReg(ARM::R4 + R, RegState::Kill) in CMSEPopCalleeSaves()
2117 BuildMI(MBB, MBBI, DL, TII.get(ARM::tPOP)).add(predOps(ARMCC::AL)); in CMSEPopCalleeSaves()
2119 PopMIB2.addReg(ARM::R4 + R, RegState::Define); in CMSEPopCalleeSaves()
2122 BuildMI(MBB, MBBI, DL, TII.get(ARM::t2LDMIA_UPD), ARM::SP) in CMSEPopCalleeSaves()
2123 .addReg(ARM::SP) in CMSEPopCalleeSaves()
2125 for (int Reg = ARM::R4; Reg < ARM::R12; ++Reg) in CMSEPopCalleeSaves()
2139 case ARM::VBSPd: in ExpandMI()
2140 case ARM::VBSPq: { in ExpandMI()
2144 unsigned NewOpc = Opcode == ARM::VBSPd ? ARM::VBITd : ARM::VBITq; in ExpandMI()
2154 unsigned NewOpc = Opcode == ARM::VBSPd ? ARM::VBIFd : ARM::VBIFq; in ExpandMI()
2164 unsigned NewOpc = Opcode == ARM::VBSPd ? ARM::VBSLd : ARM::VBSLq; in ExpandMI()
2175 unsigned MoveOpc = Opcode == ARM::VBSPd ? ARM::VORRd : ARM::VORRq; in ExpandMI()
2199 case ARM::TCRETURNdi: in ExpandMI()
2200 case ARM::TCRETURNri: in ExpandMI()
2201 case ARM::TCRETURNrinotr12: { in ExpandMI()
2203 if (MBBI->getOpcode() == ARM::SEH_EpilogEnd) in ExpandMI()
2205 if (MBBI->getOpcode() == ARM::SEH_Nop_Ret) in ExpandMI()
2216 if (MBBI->getOpcode() == ARM::SEH_EpilogEnd) in ExpandMI()
2218 if (MBBI->getOpcode() == ARM::SEH_Nop_Ret) in ExpandMI()
2223 if (RetOpcode == ARM::TCRETURNdi) { in ExpandMI()
2229 ? ((STI->isTargetMachO() || NeedsWinCFI) ? ARM::tTAILJMPd in ExpandMI()
2230 : ARM::tTAILJMPdND) in ExpandMI()
2231 : ARM::TAILJMPd; in ExpandMI()
2245 } else if (RetOpcode == ARM::TCRETURNri || in ExpandMI()
2246 RetOpcode == ARM::TCRETURNrinotr12) { in ExpandMI()
2248 STI->isThumb() ? ARM::tTAILJMPr in ExpandMI()
2249 : (STI->hasV4TOps() ? ARM::TAILJMPr : ARM::TAILJMPr4); in ExpandMI()
2271 case ARM::tBXNS_RET: { in ExpandMI()
2275 BuildMI(MBB, MBBI, DebugLoc(), TII->get(ARM::t2AUT)); in ExpandMI()
2282 TII->get(ARM::VLDR_FPCXTNS_post), ARM::SP) in ExpandMI()
2283 .addReg(ARM::SP) in ExpandMI()
2288 BuildMI(AfterBB, AfterBB.end(), DebugLoc(), TII->get(ARM::t2AUT)); in ExpandMI()
2293 return !Op.isReg() || Op.getReg() != ARM::R12; in ExpandMI()
2297 *MBBI, {ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R12}, ClearRegs); in ExpandMI()
2299 ARM::LR); in ExpandMI()
2303 TII->get(ARM::tBXNS)) in ExpandMI()
2304 .addReg(ARM::LR) in ExpandMI()
2311 case ARM::tBLXNS_CALL: { in ExpandMI()
2330 {ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, in ExpandMI()
2331 ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, in ExpandMI()
2332 ARM::R10, ARM::R11, ARM::R12}, in ExpandMI()
2342 BuildMI(MBB, MBBI, DL, TII->get(ARM::t2BICri), JumpReg) in ExpandMI()
2351 BuildMI(MBB, MBBI, DL, TII->get(ARM::tMOVi8), ScratchReg) in ExpandMI()
2355 BuildMI(MBB, MBBI, DL, TII->get(ARM::tBIC), JumpReg) in ExpandMI()
2356 .addReg(ARM::CPSR, RegState::Define) in ExpandMI()
2367 BuildMI(MBB, MBBI, DL, TII->get(ARM::tBLXNSr)) in ExpandMI()
2383 case ARM::VMOVHcc: in ExpandMI()
2384 case ARM::VMOVScc: in ExpandMI()
2385 case ARM::VMOVDcc: { in ExpandMI()
2386 unsigned newOpc = Opcode != ARM::VMOVDcc ? ARM::VMOVS : ARM::VMOVD; in ExpandMI()
2397 case ARM::t2MOVCCr: in ExpandMI()
2398 case ARM::MOVCCr: { in ExpandMI()
2399 unsigned Opc = AFI->isThumbFunction() ? ARM::t2MOVr : ARM::MOVr; in ExpandMI()
2411 case ARM::MOVCCsi: { in ExpandMI()
2412 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsi), in ExpandMI()
2424 case ARM::MOVCCsr: { in ExpandMI()
2425 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsr), in ExpandMI()
2438 case ARM::t2MOVCCi16: in ExpandMI()
2439 case ARM::MOVCCi16: { in ExpandMI()
2440 unsigned NewOpc = AFI->isThumbFunction() ? ARM::t2MOVi16 : ARM::MOVi16; in ExpandMI()
2450 case ARM::t2MOVCCi: in ExpandMI()
2451 case ARM::MOVCCi: { in ExpandMI()
2452 unsigned Opc = AFI->isThumbFunction() ? ARM::t2MOVi : ARM::MOVi; in ExpandMI()
2464 case ARM::t2MVNCCi: in ExpandMI()
2465 case ARM::MVNCCi: { in ExpandMI()
2466 unsigned Opc = AFI->isThumbFunction() ? ARM::t2MVNi : ARM::MVNi; in ExpandMI()
2478 case ARM::t2MOVCClsl: in ExpandMI()
2479 case ARM::t2MOVCClsr: in ExpandMI()
2480 case ARM::t2MOVCCasr: in ExpandMI()
2481 case ARM::t2MOVCCror: { in ExpandMI()
2484 case ARM::t2MOVCClsl: NewOpc = ARM::t2LSLri; break; in ExpandMI()
2485 case ARM::t2MOVCClsr: NewOpc = ARM::t2LSRri; break; in ExpandMI()
2486 case ARM::t2MOVCCasr: NewOpc = ARM::t2ASRri; break; in ExpandMI()
2487 case ARM::t2MOVCCror: NewOpc = ARM::t2RORri; break; in ExpandMI()
2501 case ARM::Int_eh_sjlj_dispatchsetup: { in ExpandMI()
2516 emitT2RegPlusImmediate(MBB, MBBI, MI.getDebugLoc(), ARM::R6, in ExpandMI()
2519 emitThumbRegPlusImmediate(MBB, MBBI, MI.getDebugLoc(), ARM::R6, in ExpandMI()
2522 emitARMRegPlusImmediate(MBB, MBBI, MI.getDebugLoc(), ARM::R6, in ExpandMI()
2537 ARM::t2BICri : ARM::BICri; in ExpandMI()
2538 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(bicOpc), ARM::R6) in ExpandMI()
2539 .addReg(ARM::R6, RegState::Kill) in ExpandMI()
2549 case ARM::MOVsrl_glue: in ExpandMI()
2550 case ARM::MOVsra_glue: { in ExpandMI()
2552 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsi), in ExpandMI()
2556 (Opcode == ARM::MOVsrl_glue ? ARM_AM::lsr : ARM_AM::asr), 1)) in ExpandMI()
2558 .addReg(ARM::CPSR, RegState::Define); in ExpandMI()
2562 case ARM::RRX: { in ExpandMI()
2564 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsi), in ExpandMI()
2574 case ARM::tTPsoft: in ExpandMI()
2575 case ARM::TPsoft: { in ExpandMI()
2576 const bool Thumb = Opcode == ARM::tTPsoft; in ExpandMI()
2589 TII->get(Thumb ? ARM::tLDRpci : ARM::LDRi12), Reg) in ExpandMI()
2603 TII->get(Thumb ? ARM::tBL : ARM::BL)); in ExpandMI()
2617 case ARM::tLDRpci_pic: in ExpandMI()
2618 case ARM::t2LDRpci_pic: { in ExpandMI()
2619 unsigned NewLdOpc = (Opcode == ARM::tLDRpci_pic) in ExpandMI()
2620 ? ARM::tLDRpci : ARM::t2LDRpci; in ExpandMI()
2628 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::tPICADD)) in ExpandMI()
2637 case ARM::LDRLIT_ga_abs: in ExpandMI()
2638 case ARM::LDRLIT_ga_pcrel: in ExpandMI()
2639 case ARM::LDRLIT_ga_pcrel_ldr: in ExpandMI()
2640 case ARM::tLDRLIT_ga_abs: in ExpandMI()
2641 case ARM::t2LDRLIT_ga_pcrel: in ExpandMI()
2642 case ARM::tLDRLIT_ga_pcrel: { in ExpandMI()
2648 bool IsARM = Opcode != ARM::tLDRLIT_ga_pcrel && in ExpandMI()
2649 Opcode != ARM::tLDRLIT_ga_abs && in ExpandMI()
2650 Opcode != ARM::t2LDRLIT_ga_pcrel; in ExpandMI()
2652 Opcode != ARM::LDRLIT_ga_abs && Opcode != ARM::tLDRLIT_ga_abs; in ExpandMI()
2653 unsigned LDRLITOpc = IsARM ? ARM::LDRi12 : ARM::tLDRpci; in ExpandMI()
2654 if (Opcode == ARM::t2LDRLIT_ga_pcrel) in ExpandMI()
2655 LDRLITOpc = ARM::t2LDRpci; in ExpandMI()
2658 ? (Opcode == ARM::LDRLIT_ga_pcrel_ldr ? ARM::PICLDR : ARM::PICADD) in ExpandMI()
2659 : ARM::tPICADD; in ExpandMI()
2699 case ARM::MOV_ga_pcrel: in ExpandMI()
2700 case ARM::MOV_ga_pcrel_ldr: in ExpandMI()
2701 case ARM::t2MOV_ga_pcrel: { in ExpandMI()
2709 bool isARM = Opcode != ARM::t2MOV_ga_pcrel; in ExpandMI()
2710 unsigned LO16Opc = isARM ? ARM::MOVi16_ga_pcrel : ARM::t2MOVi16_ga_pcrel; in ExpandMI()
2711 unsigned HI16Opc = isARM ? ARM::MOVTi16_ga_pcrel :ARM::t2MOVTi16_ga_pcrel; in ExpandMI()
2715 ? (Opcode == ARM::MOV_ga_pcrel_ldr ? ARM::PICLDR : ARM::PICADD) in ExpandMI()
2716 : ARM::tPICADD; in ExpandMI()
2734 if (Opcode == ARM::MOV_ga_pcrel_ldr) in ExpandMI()
2742 case ARM::MOVi32imm: in ExpandMI()
2743 case ARM::MOVCCi32imm: in ExpandMI()
2744 case ARM::t2MOVi32imm: in ExpandMI()
2745 case ARM::t2MOVCCi32imm: in ExpandMI()
2749 case ARM::tMOVi32imm: in ExpandMI()
2753 case ARM::tLEApcrelJT: in ExpandMI()
2764 case ARM::SUBS_PC_LR: { in ExpandMI()
2765 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::SUBri), ARM::PC) in ExpandMI()
2766 .addReg(ARM::LR) in ExpandMI()
2770 .addReg(ARM::CPSR, RegState::Undef) in ExpandMI()
2775 case ARM::VLDMQIA: { in ExpandMI()
2776 unsigned NewOpc = ARM::VLDMDIA; in ExpandMI()
2793 Register D0 = TRI->getSubReg(DstReg, ARM::dsub_0); in ExpandMI()
2794 Register D1 = TRI->getSubReg(DstReg, ARM::dsub_1); in ExpandMI()
2806 case ARM::VSTMQIA: { in ExpandMI()
2807 unsigned NewOpc = ARM::VSTMDIA; in ExpandMI()
2825 Register D0 = TRI->getSubReg(SrcReg, ARM::dsub_0); in ExpandMI()
2826 Register D1 = TRI->getSubReg(SrcReg, ARM::dsub_1); in ExpandMI()
2839 case ARM::VLD2q8Pseudo: in ExpandMI()
2840 case ARM::VLD2q16Pseudo: in ExpandMI()
2841 case ARM::VLD2q32Pseudo: in ExpandMI()
2842 case ARM::VLD2q8PseudoWB_fixed: in ExpandMI()
2843 case ARM::VLD2q16PseudoWB_fixed: in ExpandMI()
2844 case ARM::VLD2q32PseudoWB_fixed: in ExpandMI()
2845 case ARM::VLD2q8PseudoWB_register: in ExpandMI()
2846 case ARM::VLD2q16PseudoWB_register: in ExpandMI()
2847 case ARM::VLD2q32PseudoWB_register: in ExpandMI()
2848 case ARM::VLD3d8Pseudo: in ExpandMI()
2849 case ARM::VLD3d16Pseudo: in ExpandMI()
2850 case ARM::VLD3d32Pseudo: in ExpandMI()
2851 case ARM::VLD1d8TPseudo: in ExpandMI()
2852 case ARM::VLD1d8TPseudoWB_fixed: in ExpandMI()
2853 case ARM::VLD1d8TPseudoWB_register: in ExpandMI()
2854 case ARM::VLD1d16TPseudo: in ExpandMI()
2855 case ARM::VLD1d16TPseudoWB_fixed: in ExpandMI()
2856 case ARM::VLD1d16TPseudoWB_register: in ExpandMI()
2857 case ARM::VLD1d32TPseudo: in ExpandMI()
2858 case ARM::VLD1d32TPseudoWB_fixed: in ExpandMI()
2859 case ARM::VLD1d32TPseudoWB_register: in ExpandMI()
2860 case ARM::VLD1d64TPseudo: in ExpandMI()
2861 case ARM::VLD1d64TPseudoWB_fixed: in ExpandMI()
2862 case ARM::VLD1d64TPseudoWB_register: in ExpandMI()
2863 case ARM::VLD3d8Pseudo_UPD: in ExpandMI()
2864 case ARM::VLD3d16Pseudo_UPD: in ExpandMI()
2865 case ARM::VLD3d32Pseudo_UPD: in ExpandMI()
2866 case ARM::VLD3q8Pseudo_UPD: in ExpandMI()
2867 case ARM::VLD3q16Pseudo_UPD: in ExpandMI()
2868 case ARM::VLD3q32Pseudo_UPD: in ExpandMI()
2869 case ARM::VLD3q8oddPseudo: in ExpandMI()
2870 case ARM::VLD3q16oddPseudo: in ExpandMI()
2871 case ARM::VLD3q32oddPseudo: in ExpandMI()
2872 case ARM::VLD3q8oddPseudo_UPD: in ExpandMI()
2873 case ARM::VLD3q16oddPseudo_UPD: in ExpandMI()
2874 case ARM::VLD3q32oddPseudo_UPD: in ExpandMI()
2875 case ARM::VLD4d8Pseudo: in ExpandMI()
2876 case ARM::VLD4d16Pseudo: in ExpandMI()
2877 case ARM::VLD4d32Pseudo: in ExpandMI()
2878 case ARM::VLD1d8QPseudo: in ExpandMI()
2879 case ARM::VLD1d8QPseudoWB_fixed: in ExpandMI()
2880 case ARM::VLD1d8QPseudoWB_register: in ExpandMI()
2881 case ARM::VLD1d16QPseudo: in ExpandMI()
2882 case ARM::VLD1d16QPseudoWB_fixed: in ExpandMI()
2883 case ARM::VLD1d16QPseudoWB_register: in ExpandMI()
2884 case ARM::VLD1d32QPseudo: in ExpandMI()
2885 case ARM::VLD1d32QPseudoWB_fixed: in ExpandMI()
2886 case ARM::VLD1d32QPseudoWB_register: in ExpandMI()
2887 case ARM::VLD1d64QPseudo: in ExpandMI()
2888 case ARM::VLD1d64QPseudoWB_fixed: in ExpandMI()
2889 case ARM::VLD1d64QPseudoWB_register: in ExpandMI()
2890 case ARM::VLD1q8HighQPseudo: in ExpandMI()
2891 case ARM::VLD1q8HighQPseudo_UPD: in ExpandMI()
2892 case ARM::VLD1q8LowQPseudo_UPD: in ExpandMI()
2893 case ARM::VLD1q8HighTPseudo: in ExpandMI()
2894 case ARM::VLD1q8HighTPseudo_UPD: in ExpandMI()
2895 case ARM::VLD1q8LowTPseudo_UPD: in ExpandMI()
2896 case ARM::VLD1q16HighQPseudo: in ExpandMI()
2897 case ARM::VLD1q16HighQPseudo_UPD: in ExpandMI()
2898 case ARM::VLD1q16LowQPseudo_UPD: in ExpandMI()
2899 case ARM::VLD1q16HighTPseudo: in ExpandMI()
2900 case ARM::VLD1q16HighTPseudo_UPD: in ExpandMI()
2901 case ARM::VLD1q16LowTPseudo_UPD: in ExpandMI()
2902 case ARM::VLD1q32HighQPseudo: in ExpandMI()
2903 case ARM::VLD1q32HighQPseudo_UPD: in ExpandMI()
2904 case ARM::VLD1q32LowQPseudo_UPD: in ExpandMI()
2905 case ARM::VLD1q32HighTPseudo: in ExpandMI()
2906 case ARM::VLD1q32HighTPseudo_UPD: in ExpandMI()
2907 case ARM::VLD1q32LowTPseudo_UPD: in ExpandMI()
2908 case ARM::VLD1q64HighQPseudo: in ExpandMI()
2909 case ARM::VLD1q64HighQPseudo_UPD: in ExpandMI()
2910 case ARM::VLD1q64LowQPseudo_UPD: in ExpandMI()
2911 case ARM::VLD1q64HighTPseudo: in ExpandMI()
2912 case ARM::VLD1q64HighTPseudo_UPD: in ExpandMI()
2913 case ARM::VLD1q64LowTPseudo_UPD: in ExpandMI()
2914 case ARM::VLD4d8Pseudo_UPD: in ExpandMI()
2915 case ARM::VLD4d16Pseudo_UPD: in ExpandMI()
2916 case ARM::VLD4d32Pseudo_UPD: in ExpandMI()
2917 case ARM::VLD4q8Pseudo_UPD: in ExpandMI()
2918 case ARM::VLD4q16Pseudo_UPD: in ExpandMI()
2919 case ARM::VLD4q32Pseudo_UPD: in ExpandMI()
2920 case ARM::VLD4q8oddPseudo: in ExpandMI()
2921 case ARM::VLD4q16oddPseudo: in ExpandMI()
2922 case ARM::VLD4q32oddPseudo: in ExpandMI()
2923 case ARM::VLD4q8oddPseudo_UPD: in ExpandMI()
2924 case ARM::VLD4q16oddPseudo_UPD: in ExpandMI()
2925 case ARM::VLD4q32oddPseudo_UPD: in ExpandMI()
2926 case ARM::VLD3DUPd8Pseudo: in ExpandMI()
2927 case ARM::VLD3DUPd16Pseudo: in ExpandMI()
2928 case ARM::VLD3DUPd32Pseudo: in ExpandMI()
2929 case ARM::VLD3DUPd8Pseudo_UPD: in ExpandMI()
2930 case ARM::VLD3DUPd16Pseudo_UPD: in ExpandMI()
2931 case ARM::VLD3DUPd32Pseudo_UPD: in ExpandMI()
2932 case ARM::VLD4DUPd8Pseudo: in ExpandMI()
2933 case ARM::VLD4DUPd16Pseudo: in ExpandMI()
2934 case ARM::VLD4DUPd32Pseudo: in ExpandMI()
2935 case ARM::VLD4DUPd8Pseudo_UPD: in ExpandMI()
2936 case ARM::VLD4DUPd16Pseudo_UPD: in ExpandMI()
2937 case ARM::VLD4DUPd32Pseudo_UPD: in ExpandMI()
2938 case ARM::VLD2DUPq8EvenPseudo: in ExpandMI()
2939 case ARM::VLD2DUPq8OddPseudo: in ExpandMI()
2940 case ARM::VLD2DUPq16EvenPseudo: in ExpandMI()
2941 case ARM::VLD2DUPq16OddPseudo: in ExpandMI()
2942 case ARM::VLD2DUPq32EvenPseudo: in ExpandMI()
2943 case ARM::VLD2DUPq32OddPseudo: in ExpandMI()
2944 case ARM::VLD2DUPq8OddPseudoWB_fixed: in ExpandMI()
2945 case ARM::VLD2DUPq8OddPseudoWB_register: in ExpandMI()
2946 case ARM::VLD2DUPq16OddPseudoWB_fixed: in ExpandMI()
2947 case ARM::VLD2DUPq16OddPseudoWB_register: in ExpandMI()
2948 case ARM::VLD2DUPq32OddPseudoWB_fixed: in ExpandMI()
2949 case ARM::VLD2DUPq32OddPseudoWB_register: in ExpandMI()
2950 case ARM::VLD3DUPq8EvenPseudo: in ExpandMI()
2951 case ARM::VLD3DUPq8OddPseudo: in ExpandMI()
2952 case ARM::VLD3DUPq16EvenPseudo: in ExpandMI()
2953 case ARM::VLD3DUPq16OddPseudo: in ExpandMI()
2954 case ARM::VLD3DUPq32EvenPseudo: in ExpandMI()
2955 case ARM::VLD3DUPq32OddPseudo: in ExpandMI()
2956 case ARM::VLD3DUPq8OddPseudo_UPD: in ExpandMI()
2957 case ARM::VLD3DUPq16OddPseudo_UPD: in ExpandMI()
2958 case ARM::VLD3DUPq32OddPseudo_UPD: in ExpandMI()
2959 case ARM::VLD4DUPq8EvenPseudo: in ExpandMI()
2960 case ARM::VLD4DUPq8OddPseudo: in ExpandMI()
2961 case ARM::VLD4DUPq16EvenPseudo: in ExpandMI()
2962 case ARM::VLD4DUPq16OddPseudo: in ExpandMI()
2963 case ARM::VLD4DUPq32EvenPseudo: in ExpandMI()
2964 case ARM::VLD4DUPq32OddPseudo: in ExpandMI()
2965 case ARM::VLD4DUPq8OddPseudo_UPD: in ExpandMI()
2966 case ARM::VLD4DUPq16OddPseudo_UPD: in ExpandMI()
2967 case ARM::VLD4DUPq32OddPseudo_UPD: in ExpandMI()
2971 case ARM::VST2q8Pseudo: in ExpandMI()
2972 case ARM::VST2q16Pseudo: in ExpandMI()
2973 case ARM::VST2q32Pseudo: in ExpandMI()
2974 case ARM::VST2q8PseudoWB_fixed: in ExpandMI()
2975 case ARM::VST2q16PseudoWB_fixed: in ExpandMI()
2976 case ARM::VST2q32PseudoWB_fixed: in ExpandMI()
2977 case ARM::VST2q8PseudoWB_register: in ExpandMI()
2978 case ARM::VST2q16PseudoWB_register: in ExpandMI()
2979 case ARM::VST2q32PseudoWB_register: in ExpandMI()
2980 case ARM::VST3d8Pseudo: in ExpandMI()
2981 case ARM::VST3d16Pseudo: in ExpandMI()
2982 case ARM::VST3d32Pseudo: in ExpandMI()
2983 case ARM::VST1d8TPseudo: in ExpandMI()
2984 case ARM::VST1d8TPseudoWB_fixed: in ExpandMI()
2985 case ARM::VST1d8TPseudoWB_register: in ExpandMI()
2986 case ARM::VST1d16TPseudo: in ExpandMI()
2987 case ARM::VST1d16TPseudoWB_fixed: in ExpandMI()
2988 case ARM::VST1d16TPseudoWB_register: in ExpandMI()
2989 case ARM::VST1d32TPseudo: in ExpandMI()
2990 case ARM::VST1d32TPseudoWB_fixed: in ExpandMI()
2991 case ARM::VST1d32TPseudoWB_register: in ExpandMI()
2992 case ARM::VST1d64TPseudo: in ExpandMI()
2993 case ARM::VST1d64TPseudoWB_fixed: in ExpandMI()
2994 case ARM::VST1d64TPseudoWB_register: in ExpandMI()
2995 case ARM::VST3d8Pseudo_UPD: in ExpandMI()
2996 case ARM::VST3d16Pseudo_UPD: in ExpandMI()
2997 case ARM::VST3d32Pseudo_UPD: in ExpandMI()
2998 case ARM::VST3q8Pseudo_UPD: in ExpandMI()
2999 case ARM::VST3q16Pseudo_UPD: in ExpandMI()
3000 case ARM::VST3q32Pseudo_UPD: in ExpandMI()
3001 case ARM::VST3q8oddPseudo: in ExpandMI()
3002 case ARM::VST3q16oddPseudo: in ExpandMI()
3003 case ARM::VST3q32oddPseudo: in ExpandMI()
3004 case ARM::VST3q8oddPseudo_UPD: in ExpandMI()
3005 case ARM::VST3q16oddPseudo_UPD: in ExpandMI()
3006 case ARM::VST3q32oddPseudo_UPD: in ExpandMI()
3007 case ARM::VST4d8Pseudo: in ExpandMI()
3008 case ARM::VST4d16Pseudo: in ExpandMI()
3009 case ARM::VST4d32Pseudo: in ExpandMI()
3010 case ARM::VST1d8QPseudo: in ExpandMI()
3011 case ARM::VST1d8QPseudoWB_fixed: in ExpandMI()
3012 case ARM::VST1d8QPseudoWB_register: in ExpandMI()
3013 case ARM::VST1d16QPseudo: in ExpandMI()
3014 case ARM::VST1d16QPseudoWB_fixed: in ExpandMI()
3015 case ARM::VST1d16QPseudoWB_register: in ExpandMI()
3016 case ARM::VST1d32QPseudo: in ExpandMI()
3017 case ARM::VST1d32QPseudoWB_fixed: in ExpandMI()
3018 case ARM::VST1d32QPseudoWB_register: in ExpandMI()
3019 case ARM::VST1d64QPseudo: in ExpandMI()
3020 case ARM::VST1d64QPseudoWB_fixed: in ExpandMI()
3021 case ARM::VST1d64QPseudoWB_register: in ExpandMI()
3022 case ARM::VST4d8Pseudo_UPD: in ExpandMI()
3023 case ARM::VST4d16Pseudo_UPD: in ExpandMI()
3024 case ARM::VST4d32Pseudo_UPD: in ExpandMI()
3025 case ARM::VST1q8HighQPseudo: in ExpandMI()
3026 case ARM::VST1q8LowQPseudo_UPD: in ExpandMI()
3027 case ARM::VST1q8HighTPseudo: in ExpandMI()
3028 case ARM::VST1q8LowTPseudo_UPD: in ExpandMI()
3029 case ARM::VST1q16HighQPseudo: in ExpandMI()
3030 case ARM::VST1q16LowQPseudo_UPD: in ExpandMI()
3031 case ARM::VST1q16HighTPseudo: in ExpandMI()
3032 case ARM::VST1q16LowTPseudo_UPD: in ExpandMI()
3033 case ARM::VST1q32HighQPseudo: in ExpandMI()
3034 case ARM::VST1q32LowQPseudo_UPD: in ExpandMI()
3035 case ARM::VST1q32HighTPseudo: in ExpandMI()
3036 case ARM::VST1q32LowTPseudo_UPD: in ExpandMI()
3037 case ARM::VST1q64HighQPseudo: in ExpandMI()
3038 case ARM::VST1q64LowQPseudo_UPD: in ExpandMI()
3039 case ARM::VST1q64HighTPseudo: in ExpandMI()
3040 case ARM::VST1q64LowTPseudo_UPD: in ExpandMI()
3041 case ARM::VST1q8HighTPseudo_UPD: in ExpandMI()
3042 case ARM::VST1q16HighTPseudo_UPD: in ExpandMI()
3043 case ARM::VST1q32HighTPseudo_UPD: in ExpandMI()
3044 case ARM::VST1q64HighTPseudo_UPD: in ExpandMI()
3045 case ARM::VST1q8HighQPseudo_UPD: in ExpandMI()
3046 case ARM::VST1q16HighQPseudo_UPD: in ExpandMI()
3047 case ARM::VST1q32HighQPseudo_UPD: in ExpandMI()
3048 case ARM::VST1q64HighQPseudo_UPD: in ExpandMI()
3049 case ARM::VST4q8Pseudo_UPD: in ExpandMI()
3050 case ARM::VST4q16Pseudo_UPD: in ExpandMI()
3051 case ARM::VST4q32Pseudo_UPD: in ExpandMI()
3052 case ARM::VST4q8oddPseudo: in ExpandMI()
3053 case ARM::VST4q16oddPseudo: in ExpandMI()
3054 case ARM::VST4q32oddPseudo: in ExpandMI()
3055 case ARM::VST4q8oddPseudo_UPD: in ExpandMI()
3056 case ARM::VST4q16oddPseudo_UPD: in ExpandMI()
3057 case ARM::VST4q32oddPseudo_UPD: in ExpandMI()
3061 case ARM::VLD1LNq8Pseudo: in ExpandMI()
3062 case ARM::VLD1LNq16Pseudo: in ExpandMI()
3063 case ARM::VLD1LNq32Pseudo: in ExpandMI()
3064 case ARM::VLD1LNq8Pseudo_UPD: in ExpandMI()
3065 case ARM::VLD1LNq16Pseudo_UPD: in ExpandMI()
3066 case ARM::VLD1LNq32Pseudo_UPD: in ExpandMI()
3067 case ARM::VLD2LNd8Pseudo: in ExpandMI()
3068 case ARM::VLD2LNd16Pseudo: in ExpandMI()
3069 case ARM::VLD2LNd32Pseudo: in ExpandMI()
3070 case ARM::VLD2LNq16Pseudo: in ExpandMI()
3071 case ARM::VLD2LNq32Pseudo: in ExpandMI()
3072 case ARM::VLD2LNd8Pseudo_UPD: in ExpandMI()
3073 case ARM::VLD2LNd16Pseudo_UPD: in ExpandMI()
3074 case ARM::VLD2LNd32Pseudo_UPD: in ExpandMI()
3075 case ARM::VLD2LNq16Pseudo_UPD: in ExpandMI()
3076 case ARM::VLD2LNq32Pseudo_UPD: in ExpandMI()
3077 case ARM::VLD3LNd8Pseudo: in ExpandMI()
3078 case ARM::VLD3LNd16Pseudo: in ExpandMI()
3079 case ARM::VLD3LNd32Pseudo: in ExpandMI()
3080 case ARM::VLD3LNq16Pseudo: in ExpandMI()
3081 case ARM::VLD3LNq32Pseudo: in ExpandMI()
3082 case ARM::VLD3LNd8Pseudo_UPD: in ExpandMI()
3083 case ARM::VLD3LNd16Pseudo_UPD: in ExpandMI()
3084 case ARM::VLD3LNd32Pseudo_UPD: in ExpandMI()
3085 case ARM::VLD3LNq16Pseudo_UPD: in ExpandMI()
3086 case ARM::VLD3LNq32Pseudo_UPD: in ExpandMI()
3087 case ARM::VLD4LNd8Pseudo: in ExpandMI()
3088 case ARM::VLD4LNd16Pseudo: in ExpandMI()
3089 case ARM::VLD4LNd32Pseudo: in ExpandMI()
3090 case ARM::VLD4LNq16Pseudo: in ExpandMI()
3091 case ARM::VLD4LNq32Pseudo: in ExpandMI()
3092 case ARM::VLD4LNd8Pseudo_UPD: in ExpandMI()
3093 case ARM::VLD4LNd16Pseudo_UPD: in ExpandMI()
3094 case ARM::VLD4LNd32Pseudo_UPD: in ExpandMI()
3095 case ARM::VLD4LNq16Pseudo_UPD: in ExpandMI()
3096 case ARM::VLD4LNq32Pseudo_UPD: in ExpandMI()
3097 case ARM::VST1LNq8Pseudo: in ExpandMI()
3098 case ARM::VST1LNq16Pseudo: in ExpandMI()
3099 case ARM::VST1LNq32Pseudo: in ExpandMI()
3100 case ARM::VST1LNq8Pseudo_UPD: in ExpandMI()
3101 case ARM::VST1LNq16Pseudo_UPD: in ExpandMI()
3102 case ARM::VST1LNq32Pseudo_UPD: in ExpandMI()
3103 case ARM::VST2LNd8Pseudo: in ExpandMI()
3104 case ARM::VST2LNd16Pseudo: in ExpandMI()
3105 case ARM::VST2LNd32Pseudo: in ExpandMI()
3106 case ARM::VST2LNq16Pseudo: in ExpandMI()
3107 case ARM::VST2LNq32Pseudo: in ExpandMI()
3108 case ARM::VST2LNd8Pseudo_UPD: in ExpandMI()
3109 case ARM::VST2LNd16Pseudo_UPD: in ExpandMI()
3110 case ARM::VST2LNd32Pseudo_UPD: in ExpandMI()
3111 case ARM::VST2LNq16Pseudo_UPD: in ExpandMI()
3112 case ARM::VST2LNq32Pseudo_UPD: in ExpandMI()
3113 case ARM::VST3LNd8Pseudo: in ExpandMI()
3114 case ARM::VST3LNd16Pseudo: in ExpandMI()
3115 case ARM::VST3LNd32Pseudo: in ExpandMI()
3116 case ARM::VST3LNq16Pseudo: in ExpandMI()
3117 case ARM::VST3LNq32Pseudo: in ExpandMI()
3118 case ARM::VST3LNd8Pseudo_UPD: in ExpandMI()
3119 case ARM::VST3LNd16Pseudo_UPD: in ExpandMI()
3120 case ARM::VST3LNd32Pseudo_UPD: in ExpandMI()
3121 case ARM::VST3LNq16Pseudo_UPD: in ExpandMI()
3122 case ARM::VST3LNq32Pseudo_UPD: in ExpandMI()
3123 case ARM::VST4LNd8Pseudo: in ExpandMI()
3124 case ARM::VST4LNd16Pseudo: in ExpandMI()
3125 case ARM::VST4LNd32Pseudo: in ExpandMI()
3126 case ARM::VST4LNq16Pseudo: in ExpandMI()
3127 case ARM::VST4LNq32Pseudo: in ExpandMI()
3128 case ARM::VST4LNd8Pseudo_UPD: in ExpandMI()
3129 case ARM::VST4LNd16Pseudo_UPD: in ExpandMI()
3130 case ARM::VST4LNd32Pseudo_UPD: in ExpandMI()
3131 case ARM::VST4LNq16Pseudo_UPD: in ExpandMI()
3132 case ARM::VST4LNq32Pseudo_UPD: in ExpandMI()
3136 case ARM::VTBL3Pseudo: ExpandVTBL(MBBI, ARM::VTBL3, false); return true; in ExpandMI()
3137 case ARM::VTBL4Pseudo: ExpandVTBL(MBBI, ARM::VTBL4, false); return true; in ExpandMI()
3138 case ARM::VTBX3Pseudo: ExpandVTBL(MBBI, ARM::VTBX3, true); return true; in ExpandMI()
3139 case ARM::VTBX4Pseudo: ExpandVTBL(MBBI, ARM::VTBX4, true); return true; in ExpandMI()
3141 case ARM::MQQPRLoad: in ExpandMI()
3142 case ARM::MQQPRStore: in ExpandMI()
3143 case ARM::MQQQQPRLoad: in ExpandMI()
3144 case ARM::MQQQQPRStore: in ExpandMI()
3148 case ARM::tCMP_SWAP_8: in ExpandMI()
3150 return ExpandCMP_SWAP(MBB, MBBI, ARM::t2LDREXB, ARM::t2STREXB, ARM::tUXTB, in ExpandMI()
3152 case ARM::tCMP_SWAP_16: in ExpandMI()
3154 return ExpandCMP_SWAP(MBB, MBBI, ARM::t2LDREXH, ARM::t2STREXH, ARM::tUXTH, in ExpandMI()
3156 case ARM::tCMP_SWAP_32: in ExpandMI()
3158 return ExpandCMP_SWAP(MBB, MBBI, ARM::t2LDREX, ARM::t2STREX, 0, NextMBBI); in ExpandMI()
3160 case ARM::CMP_SWAP_8: in ExpandMI()
3162 return ExpandCMP_SWAP(MBB, MBBI, ARM::LDREXB, ARM::STREXB, ARM::UXTB, in ExpandMI()
3164 case ARM::CMP_SWAP_16: in ExpandMI()
3166 return ExpandCMP_SWAP(MBB, MBBI, ARM::LDREXH, ARM::STREXH, ARM::UXTH, in ExpandMI()
3168 case ARM::CMP_SWAP_32: in ExpandMI()
3170 return ExpandCMP_SWAP(MBB, MBBI, ARM::LDREX, ARM::STREX, 0, NextMBBI); in ExpandMI()
3172 case ARM::CMP_SWAP_64: in ExpandMI()
3175 case ARM::tBL_PUSHLR: in ExpandMI()
3176 case ARM::BL_PUSHLR: { in ExpandMI()
3177 const bool Thumb = Opcode == ARM::tBL_PUSHLR; in ExpandMI()
3179 assert(Reg == ARM::LR && "expect LR register!"); in ExpandMI()
3183 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::tPUSH)) in ExpandMI()
3188 MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::tBL)); in ExpandMI()
3191 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::STMDB_UPD)) in ExpandMI()
3192 .addReg(ARM::SP, RegState::Define) in ExpandMI()
3193 .addReg(ARM::SP) in ExpandMI()
3198 MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::BL)); in ExpandMI()
3206 case ARM::t2CALL_BTI: { in ExpandMI()
3209 BuildMI(MF, MI.getDebugLoc(), TII->get(ARM::tBL)); in ExpandMI()
3217 Bundler.append(BuildMI(MF, MI.getDebugLoc(), TII->get(ARM::t2BTI))); in ExpandMI()
3222 case ARM::LOADDUAL: in ExpandMI()
3223 case ARM::STOREDUAL: { in ExpandMI()
3228 TII->get(Opcode == ARM::LOADDUAL ? ARM::LDRD : ARM::STRD)) in ExpandMI()
3229 .addReg(TRI->getSubReg(PairReg, ARM::gsub_0), in ExpandMI()
3230 Opcode == ARM::LOADDUAL ? RegState::Define : 0) in ExpandMI()
3231 .addReg(TRI->getSubReg(PairReg, ARM::gsub_1), in ExpandMI()
3232 Opcode == ARM::LOADDUAL ? RegState::Define : 0); in ExpandMI()
3262 LLVM_DEBUG(dbgs() << "********** ARM EXPAND PSEUDO INSTRUCTIONS **********\n" in runOnMachineFunction()
3269 MF.verify(this, "After expanding ARM pseudo instructions."); in runOnMachineFunction()