85   if (VTSize == 64)  in isSupportedType()
98                           MachineRegisterInfo &MRI, MachineInstrBuilder &MIB)  in ARMOutgoingValueHandler()
99       : OutgoingValueHandler(MIRBuilder, MRI), MIB(MIB) {}  in ARMOutgoingValueHandler()
124     assert(VA.getValVT().getSizeInBits() <= 64 && "Unsupported value size");  in assignValueToReg()
125     assert(VA.getLocVT().getSizeInBits() <= 64 && "Unsupported location size");  in assignValueToReg()
129     MIB.addUse(PhysReg, RegState::Implicit);  in assignValueToReg()
183   MachineInstrBuilder MIB;  member
300     assert(ValSize <= 64 && "Unsupported value size");  in assignValueToReg()
301     assert(LocSize <= 64 && "Unsupported location size");  in assignValueToReg()
434                     MachineInstrBuilder MIB)  in CallReturnHandler()
435       : ARMIncomingValueHandler(MIRBuilder, MRI), MIB(MIB) {}  in CallReturnHandler()
438     MIB.addDef(PhysReg, RegState::Implicit);  in markPhysRegUsed()
441   MachineInstrBuilder MIB;  member
483   auto MIB = MIRBuilder.buildInstrNoInsert(CallOpcode);  in lowerCall()  local
487     MIB.add(predOps(ARMCC::AL));  in lowerCall()
489   MIB.add(Info.Callee);  in lowerCall()
494       MIB->getOperand(CalleeIdx).setReg(constrainOperandRegClass(  in lowerCall()
496           *MIB.getInstr(), MIB->getDesc(), Info.Callee, CalleeIdx));  in lowerCall()
500   MIB.addRegMask(TRI->getCallPreservedMask(MF, Info.CallConv));  in lowerCall()
515   ARMOutgoingValueHandler ArgHandler(MIRBuilder, MRI, MIB);  in lowerCall()
521   MIRBuilder.insertInstr(MIB);  in lowerCall()
531     CallReturnHandler RetHandler(MIRBuilder, MRI, MIB);  in lowerCall()