Lines Matching +full:fiq +full:- +full:based
1 //===-- ARMBaseRegisterInfo.cpp - ARM Register Information ----------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
50 #define DEBUG_TYPE "arm-register-info"
64 const ARMSubtarget &STI = MF->getSubtarget<ARMSubtarget>(); in getCalleeSavedRegs()
66 const Function &F = MF->getFunction(); in getCalleeSavedRegs()
83 // M-class CPUs have hardware which saves the registers needed to allow a in getCalleeSavedRegs()
86 } else if (F.getFnAttribute("interrupt").getValueAsString() == "FIQ") { in getCalleeSavedRegs()
87 // Fast interrupt mode gives the handler a private copy of R8-R14, so less in getCalleeSavedRegs()
88 // need to be saved to restore user-mode state. in getCalleeSavedRegs()
91 // Generally only R13-R14 (i.e. SP, LR) are automatically preserved by in getCalleeSavedRegs()
97 if (STI.getTargetLowering()->supportSwiftError() && in getCalleeSavedRegs()
107 return MF->getInfo<ARMFunctionInfo>()->isSplitCSR() in getCalleeSavedRegs()
124 if (MF->getFunction().getCallingConv() == CallingConv::CXX_FAST_TLS && in getCalleeSavedRegsViaCopy()
125 MF->getInfo<ARMFunctionInfo>()->isSplitCSR()) in getCalleeSavedRegsViaCopy()
143 if (STI.getTargetLowering()->supportSwiftError() && in getCallPreservedMask()
204 // FIXME: avoid re-calculating this every time. in getReservedRegs()
210 if (TFI->isFPReserved(MF)) in getReservedRegs()
217 // Reserve D16-D31 if the subtarget doesn't support them. in getReservedRegs()
247 if (TFI->isFPReserved(MF)) in isInlineAsmReadOnlyReg()
259 TargetRegisterClass::sc_iterator I = RC->getSuperClasses(); in getLargestLegalSuperClass()
261 switch (Super->getID()) { in getLargestLegalSuperClass()
304 switch (RC->getID()) { in getRegPressureLimit()
312 ? TFI->hasFP(MF) : true; in getRegPressureLimit()
313 return 5 - HasFP; in getRegPressureLimit()
317 ? TFI->hasFP(MF) : true; in getRegPressureLimit()
318 return 10 - HasFP - (STI.isR9Reserved() ? 1 : 0); in getRegPressureLimit()
322 return 32 - 10; in getRegPressureLimit()
329 for (MCPhysReg Super : RI->superregs(Reg)) in getPairedGPR()
331 return RI->getSubReg(Super, Odd ? ARM::gsub_1 : ARM::gsub_0); in getPairedGPR()
353 if (MRI.getRegClass(VirtReg)->contains(ARM::LR)) in getRegAllocationHints()
370 } else if (VRM && VRM->hasPhys(Paired)) { in getRegAllocationHints()
371 PairedPhys = getPairedGPR(VRM->getPhys(Paired), Odd, this); in getRegAllocationHints()
394 std::pair<unsigned, Register> Hint = MRI->getRegAllocationHint(Reg); in updateRegAllocHint()
402 Hint = MRI->getRegAllocationHint(OtherReg); in updateRegAllocHint()
405 MRI->setRegAllocationHint(OtherReg, Hint.first, NewReg); in updateRegAllocHint()
407 MRI->setRegAllocationHint(NewReg, in updateRegAllocHint()
424 if (hasStackRealignment(MF) && !TFI->hasReservedCallFrame(MF)) in hasBasePointer()
441 if (AFI->isThumb2Function() && MFI.hasVarSizedObjects() && in hasBasePointer()
448 if (AFI->isThumb1OnlyFunction() && !TFI->hasReservedCallFrame(MF)) in hasBasePointer()
464 if (!MRI->canReserveReg(STI.getFramePointerReg())) in canRealignStack()
468 if (TFI->hasReservedCallFrame(MF)) in canRealignStack()
472 return MRI->canReserveReg(BasePtr); in canRealignStack()
489 if (TFI->hasFP(MF)) in getFrameRegister()
494 /// emitLoadConstPool - Emits a load from constpool to materialize the
505 unsigned Idx = ConstantPool->getConstantPoolIndex(C, Align(4)); in emitLoadConstPool()
532 const MCInstrDesc &Desc = MI->getDesc(); in getFrameIndexInstrOffset()
543 InstrOffs = MI->getOperand(Idx+1).getImm(); in getFrameIndexInstrOffset()
548 const MachineOperand &OffOp = MI->getOperand(Idx+1); in getFrameIndexInstrOffset()
551 InstrOffs = -InstrOffs; in getFrameIndexInstrOffset()
557 InstrOffs = ARM_AM::getAM2Offset(MI->getOperand(ImmIdx).getImm()); in getFrameIndexInstrOffset()
558 if (ARM_AM::getAM2Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub) in getFrameIndexInstrOffset()
559 InstrOffs = -InstrOffs; in getFrameIndexInstrOffset()
563 InstrOffs = ARM_AM::getAM3Offset(MI->getOperand(ImmIdx).getImm()); in getFrameIndexInstrOffset()
564 if (ARM_AM::getAM3Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub) in getFrameIndexInstrOffset()
565 InstrOffs = -InstrOffs; in getFrameIndexInstrOffset()
569 InstrOffs = MI->getOperand(ImmIdx).getImm(); in getFrameIndexInstrOffset()
579 /// needsFrameBaseReg - Returns true if the instruction's frame index
585 for (unsigned i = 0; !MI->getOperand(i).isFI(); ++i) { in needsFrameBaseReg()
586 assert(i < MI->getNumOperands() &&"Instr doesn't have FrameIndex operand!"); in needsFrameBaseReg()
591 // based on the size of the local frame and some conservative assumptions in needsFrameBaseReg()
592 // about the rest of the stack frame (note, this is pre-regalloc, so in needsFrameBaseReg()
598 unsigned Opc = MI->getOpcode(); in needsFrameBaseReg()
613 // objects, all fixed-size local references will be via the frame pointer, in needsFrameBaseReg()
615 // Note that the incoming offset is based on the SP value at function entry, in needsFrameBaseReg()
617 MachineFunction &MF = *MI->getParent()->getParent(); in needsFrameBaseReg()
623 // Conservatively assume all callee-saved registers get pushed. R4-R6 in needsFrameBaseReg()
626 int64_t FPOffset = Offset - 8; in needsFrameBaseReg()
627 // ARM and Thumb2 functions also need to consider R8-R11 and D8-D15 in needsFrameBaseReg()
628 if (!AFI->isThumbFunction() || !AFI->isThumb1OnlyFunction()) in needsFrameBaseReg()
629 FPOffset -= 80; in needsFrameBaseReg()
633 // allocation, so adjust our SP-relative offset by that allocation size. in needsFrameBaseReg()
642 // don't know for sure yet whether we'll need that, so we guess based in needsFrameBaseReg()
644 if (TFI->hasFP(MF) && in needsFrameBaseReg()
645 !((MFI.getLocalFrameMaxAlign() > TFI->getStackAlign()) && in needsFrameBaseReg()
662 /// materializeFrameBaseRegister - Insert defining instruction(s) for BaseReg to
668 ARMFunctionInfo *AFI = MBB->getParent()->getInfo<ARMFunctionInfo>(); in materializeFrameBaseRegister()
669 unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri : in materializeFrameBaseRegister()
670 (AFI->isThumb1OnlyFunction() ? ARM::tADDframe : ARM::t2ADDri); in materializeFrameBaseRegister()
672 MachineBasicBlock::iterator Ins = MBB->begin(); in materializeFrameBaseRegister()
674 if (Ins != MBB->end()) in materializeFrameBaseRegister()
675 DL = Ins->getDebugLoc(); in materializeFrameBaseRegister()
677 const MachineFunction &MF = *MBB->getParent(); in materializeFrameBaseRegister()
678 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo(); in materializeFrameBaseRegister()
687 if (!AFI->isThumb1OnlyFunction()) in materializeFrameBaseRegister()
700 int Off = Offset; // ARM doesn't need the general 64-bit offsets in resolveFrameIndex()
703 assert(!AFI->isThumb1OnlyFunction() && in resolveFrameIndex()
711 if (!AFI->isThumbFunction()) in resolveFrameIndex()
714 assert(AFI->isThumb2Function()); in resolveFrameIndex()
724 const MCInstrDesc &Desc = MI->getDesc(); in isFrameOffsetLegal()
727 for (; !MI->getOperand(i).isFI(); ++i) in isFrameOffsetLegal()
728 assert(i+1 < MI->getNumOperands() && "Instr doesn't have FrameIndex operand!"); in isFrameOffsetLegal()
743 // based on Offset sign, consider the appropriate instruction in isFrameOffsetLegal()
747 Offset = -Offset; in isFrameOffsetLegal()
776 if ((Offset & (Scale-1)) != 0) in isFrameOffsetLegal()
780 Offset = -Offset; in isFrameOffsetLegal()
782 unsigned Mask = (1 << NumBits) - 1; in isFrameOffsetLegal()
800 assert(!AFI->isThumb1OnlyFunction() && in eliminateFrameIndex()
805 int Offset = TFI->ResolveFrameIndexReference(MF, FrameIndex, FrameReg, SPAdj); in eliminateFrameIndex()
812 if (RS && FrameReg == ARM::SP && RS->isScavengingFrameIndex(FrameIndex)){ in eliminateFrameIndex()
813 assert(TFI->hasReservedCallFrame(MF) && in eliminateFrameIndex()
822 assert(!MI.isDebugValue() && "DBG_VALUEs should be handled in target-independent code"); in eliminateFrameIndex()
826 if (!AFI->isThumbFunction()) in eliminateFrameIndex()
829 assert(AFI->isThumb2Function()); in eliminateFrameIndex()
850 ARMCC::CondCodes Pred = (PIdx == -1) in eliminateFrameIndex()
852 Register PredReg = (PIdx == -1) ? Register() : MI.getOperand(PIdx+1).getReg(); in eliminateFrameIndex()
856 TII.getRegClass(MCID, FIOperandNum, this, *MI.getParent()->getParent()); in eliminateFrameIndex()
858 if (Offset == 0 && (FrameReg.isVirtual() || RegClass->contains(FrameReg))) in eliminateFrameIndex()
863 if (!AFI->isThumbFunction()) in eliminateFrameIndex()
867 assert(AFI->isThumb2Function()); in eliminateFrameIndex()
884 auto MBB = MI->getParent(); in shouldCoalesce()
885 auto MF = MBB->getParent(); in shouldCoalesce()
886 const MachineRegisterInfo &MRI = MF->getRegInfo(); in shouldCoalesce()
887 // If not copying into a sub-register this should be ok because we shouldn't in shouldCoalesce()
897 MRI.getTargetRegisterInfo()->getRegClassWeight(NewRC); in shouldCoalesce()
899 MRI.getTargetRegisterInfo()->getRegClassWeight(SrcRC); in shouldCoalesce()
901 MRI.getTargetRegisterInfo()->getRegClassWeight(DstRC); in shouldCoalesce()
913 auto AFI = MF->getInfo<ARMFunctionInfo>(); in shouldCoalesce()
914 auto It = AFI->getCoalescedWeight(MBB); in shouldCoalesce()
916 LLVM_DEBUG(dbgs() << "\tARM::shouldCoalesce - Coalesced Weight: " in shouldCoalesce()
917 << It->second << "\n"); in shouldCoalesce()
918 LLVM_DEBUG(dbgs() << "\tARM::shouldCoalesce - Reg Weight: " in shouldCoalesce()
923 // (2) generates better code in some test cases (like vldm-shed-a9.ll) in shouldCoalesce()
924 // (3) Doesn't regress any test cases (in-tree, test-suite, and SPEC) in shouldCoalesce()
927 unsigned SizeMultiplier = MBB->size()/100; in shouldCoalesce()
929 if (It->second < NewRCWeight.WeightLimit * SizeMultiplier) { in shouldCoalesce()
930 It->second += NewRCWeight.RegWeight; in shouldCoalesce()