1 //===-- ARMBaseInstrInfo.h - ARM Base Instruction Information ---*- C++ -*-===//
9 // This file contains the Base ARM implementation of the TargetInstrInfo class.
116   /// enhance debug entry value descriptions for ARM targets.
355   /// ARM supports the MachineOutliner.
377     return MI->getOpcode() == ARM::t2LoopEndDec ||  in isUnspillableTerminatorImpl()
378            MI->getOpcode() == ARM::t2DoLoopStartTP ||  in isUnspillableTerminatorImpl()
379            MI->getOpcode() == ARM::t2WhileLoopStartLR ||  in isUnspillableTerminatorImpl()
380            MI->getOpcode() == ARM::t2WhileLoopStartTP;  in isUnspillableTerminatorImpl()
546     if (RegClassID == ARM::MQPRRegClass.getID())  in getUndefInitOpcode()
547       return ARM::PseudoARMInitUndefMQPR;  in getUndefInitOpcode()
548     if (RegClassID == ARM::SPRRegClass.getID())  in getUndefInitOpcode()
549       return ARM::PseudoARMInitUndefSPR;  in getUndefInitOpcode()
550     if (RegClassID == ARM::DPR_VFP2RegClass.getID())  in getUndefInitOpcode()
551       return ARM::PseudoARMInitUndefDPR_VFP2;  in getUndefInitOpcode()
552     if (RegClassID == ARM::GPRRegClass.getID())  in getUndefInitOpcode()
553       return ARM::PseudoARMInitUndefGPR;  in getUndefInitOpcode()
578   return MachineOperand::CreateReg(ARM::CPSR,
585   return Opc == ARM::B || Opc == ARM::tB || Opc == ARM::t2B;  in isUncondBranchOpcode()
592   return Opc == ARM::MVE_VPTv16i8 || Opc == ARM::MVE_VPTv16u8 ||  in isVPTOpcode()
593          Opc == ARM::MVE_VPTv16s8 || Opc == ARM::MVE_VPTv8i16 ||  in isVPTOpcode()
594          Opc == ARM::MVE_VPTv8u16 || Opc == ARM::MVE_VPTv8s16 ||  in isVPTOpcode()
595          Opc == ARM::MVE_VPTv4i32 || Opc == ARM::MVE_VPTv4u32 ||  in isVPTOpcode()
596          Opc == ARM::MVE_VPTv4s32 || Opc == ARM::MVE_VPTv4f32 ||  in isVPTOpcode()
597          Opc == ARM::MVE_VPTv8f16 || Opc == ARM::MVE_VPTv16i8r ||  in isVPTOpcode()
598          Opc == ARM::MVE_VPTv16u8r || Opc == ARM::MVE_VPTv16s8r ||  in isVPTOpcode()
599          Opc == ARM::MVE_VPTv8i16r || Opc == ARM::MVE_VPTv8u16r ||  in isVPTOpcode()
600          Opc == ARM::MVE_VPTv8s16r || Opc == ARM::MVE_VPTv4i32r ||  in isVPTOpcode()
601          Opc == ARM::MVE_VPTv4u32r || Opc == ARM::MVE_VPTv4s32r ||  in isVPTOpcode()
602          Opc == ARM::MVE_VPTv4f32r || Opc == ARM::MVE_VPTv8f16r ||  in isVPTOpcode()
603          Opc == ARM::MVE_VPST;  in isVPTOpcode()
611   case ARM::MVE_VCMPf32:  in VCMPOpcodeToVPT()
612     return ARM::MVE_VPTv4f32;  in VCMPOpcodeToVPT()
613   case ARM::MVE_VCMPf16:  in VCMPOpcodeToVPT()
614     return ARM::MVE_VPTv8f16;  in VCMPOpcodeToVPT()
615   case ARM::MVE_VCMPi8:  in VCMPOpcodeToVPT()
616     return ARM::MVE_VPTv16i8;  in VCMPOpcodeToVPT()
617   case ARM::MVE_VCMPi16:  in VCMPOpcodeToVPT()
618     return ARM::MVE_VPTv8i16;  in VCMPOpcodeToVPT()
619   case ARM::MVE_VCMPi32:  in VCMPOpcodeToVPT()
620     return ARM::MVE_VPTv4i32;  in VCMPOpcodeToVPT()
621   case ARM::MVE_VCMPu8:  in VCMPOpcodeToVPT()
622     return ARM::MVE_VPTv16u8;  in VCMPOpcodeToVPT()
623   case ARM::MVE_VCMPu16:  in VCMPOpcodeToVPT()
624     return ARM::MVE_VPTv8u16;  in VCMPOpcodeToVPT()
625   case ARM::MVE_VCMPu32:  in VCMPOpcodeToVPT()
626     return ARM::MVE_VPTv4u32;  in VCMPOpcodeToVPT()
627   case ARM::MVE_VCMPs8:  in VCMPOpcodeToVPT()
628     return ARM::MVE_VPTv16s8;  in VCMPOpcodeToVPT()
629   case ARM::MVE_VCMPs16:  in VCMPOpcodeToVPT()
630     return ARM::MVE_VPTv8s16;  in VCMPOpcodeToVPT()
631   case ARM::MVE_VCMPs32:  in VCMPOpcodeToVPT()
632     return ARM::MVE_VPTv4s32;  in VCMPOpcodeToVPT()
634   case ARM::MVE_VCMPf32r:  in VCMPOpcodeToVPT()
635     return ARM::MVE_VPTv4f32r;  in VCMPOpcodeToVPT()
636   case ARM::MVE_VCMPf16r:  in VCMPOpcodeToVPT()
637     return ARM::MVE_VPTv8f16r;  in VCMPOpcodeToVPT()
638   case ARM::MVE_VCMPi8r:  in VCMPOpcodeToVPT()
639     return ARM::MVE_VPTv16i8r;  in VCMPOpcodeToVPT()
640   case ARM::MVE_VCMPi16r:  in VCMPOpcodeToVPT()
641     return ARM::MVE_VPTv8i16r;  in VCMPOpcodeToVPT()
642   case ARM::MVE_VCMPi32r:  in VCMPOpcodeToVPT()
643     return ARM::MVE_VPTv4i32r;  in VCMPOpcodeToVPT()
644   case ARM::MVE_VCMPu8r:  in VCMPOpcodeToVPT()
645     return ARM::MVE_VPTv16u8r;  in VCMPOpcodeToVPT()
646   case ARM::MVE_VCMPu16r:  in VCMPOpcodeToVPT()
647     return ARM::MVE_VPTv8u16r;  in VCMPOpcodeToVPT()
648   case ARM::MVE_VCMPu32r:  in VCMPOpcodeToVPT()
649     return ARM::MVE_VPTv4u32r;  in VCMPOpcodeToVPT()
650   case ARM::MVE_VCMPs8r:  in VCMPOpcodeToVPT()
651     return ARM::MVE_VPTv16s8r;  in VCMPOpcodeToVPT()
652   case ARM::MVE_VCMPs16r:  in VCMPOpcodeToVPT()
653     return ARM::MVE_VPTv8s16r;  in VCMPOpcodeToVPT()
654   case ARM::MVE_VCMPs32r:  in VCMPOpcodeToVPT()
655     return ARM::MVE_VPTv4s32r;  in VCMPOpcodeToVPT()
661   return Opc == ARM::Bcc || Opc == ARM::tBcc || Opc == ARM::t2Bcc;  in isCondBranchOpcode()
665   return Opc == ARM::BR_JTr || Opc == ARM::BR_JTm_i12 ||  in isJumpTableBranchOpcode()
666          Opc == ARM::BR_JTm_rs || Opc == ARM::BR_JTadd || Opc == ARM::tBR_JTr ||  in isJumpTableBranchOpcode()
667          Opc == ARM::t2BR_JT;  in isJumpTableBranchOpcode()
672   return Opc == ARM::BX || Opc == ARM::MOVPCRX || Opc == ARM::tBRIND;  in isIndirectBranchOpcode()
679   case ARM::BLX:  in isIndirectCall()
680   case ARM::BLX_noip:  in isIndirectCall()
681   case ARM::BLX_pred:  in isIndirectCall()
682   case ARM::BLX_pred_noip:  in isIndirectCall()
683   case ARM::BX_CALL:  in isIndirectCall()
684   case ARM::BMOVPCRX_CALL:  in isIndirectCall()
685   case ARM::TCRETURNri:  in isIndirectCall()
686   case ARM::TCRETURNrinotr12:  in isIndirectCall()
687   case ARM::TAILJMPr:  in isIndirectCall()
688   case ARM::TAILJMPr4:  in isIndirectCall()
689   case ARM::tBLXr:  in isIndirectCall()
690   case ARM::tBLXr_noip:  in isIndirectCall()
691   case ARM::tBLXNSr:  in isIndirectCall()
692   case ARM::tBLXNS_CALL:  in isIndirectCall()
693   case ARM::tBX_CALL:  in isIndirectCall()
694   case ARM::tTAILJMPr:  in isIndirectCall()
698   case ARM::BL:  in isIndirectCall()
699   case ARM::BL_pred:  in isIndirectCall()
700   case ARM::BMOVPCB_CALL:  in isIndirectCall()
701   case ARM::BL_PUSHLR:  in isIndirectCall()
702   case ARM::BLXi:  in isIndirectCall()
703   case ARM::TCRETURNdi:  in isIndirectCall()
704   case ARM::TAILJMPd:  in isIndirectCall()
705   case ARM::SVC:  in isIndirectCall()
706   case ARM::HVC:  in isIndirectCall()
707   case ARM::TPsoft:  in isIndirectCall()
708   case ARM::tTAILJMPd:  in isIndirectCall()
709   case ARM::t2SMC:  in isIndirectCall()
710   case ARM::t2HVC:  in isIndirectCall()
711   case ARM::tBL:  in isIndirectCall()
712   case ARM::tBLXi:  in isIndirectCall()
713   case ARM::tBL_PUSHLR:  in isIndirectCall()
714   case ARM::tTAILJMPdND:  in isIndirectCall()
715   case ARM::tSVC:  in isIndirectCall()
716   case ARM::tTPsoft:  in isIndirectCall()
731   return Opc == ARM::SpeculationBarrierISBDSBEndBB ||  in isSpeculationBarrierEndBBOpcode()
732          Opc == ARM::SpeculationBarrierSBEndBB ||  in isSpeculationBarrierEndBBOpcode()
733          Opc == ARM::t2SpeculationBarrierISBDSBEndBB ||  in isSpeculationBarrierEndBBOpcode()
734          Opc == ARM::t2SpeculationBarrierSBEndBB;  in isSpeculationBarrierEndBBOpcode()
738   return Opc == ARM::tPOP_RET || Opc == ARM::LDMIA_RET ||  in isPopOpcode()
739          Opc == ARM::t2LDMIA_RET || Opc == ARM::tPOP || Opc == ARM::LDMIA_UPD ||  in isPopOpcode()
740          Opc == ARM::t2LDMIA_UPD || Opc == ARM::VLDMDIA_UPD;  in isPopOpcode()
744   return Opc == ARM::tPUSH || Opc == ARM::t2STMDB_UPD ||  in isPushOpcode()
745          Opc == ARM::STMDB_UPD || Opc == ARM::VSTMDDB_UPD;  in isPushOpcode()
749   return Opc == ARM::SUBri ||  in isSubImmOpcode()
750          Opc == ARM::tSUBi3 || Opc == ARM::tSUBi8 ||  in isSubImmOpcode()
751          Opc == ARM::tSUBSi3 || Opc == ARM::tSUBSi8 ||  in isSubImmOpcode()
752          Opc == ARM::t2SUBri || Opc == ARM::t2SUBri12 || Opc == ARM::t2SUBSri;  in isSubImmOpcode()
756   return Opc == ARM::MOVr || Opc == ARM::tMOVr || Opc == ARM::t2MOVr;  in isMovRegOpcode()
769   if (featureBits[ARM::HasV8Ops] && (Num & 0xE) != 0xE)  in isValidCoprocessorNumber()
774   if (featureBits[ARM::HasV8_1MMainlineOps] &&  in isValidCoprocessorNumber()
784   case ARM::SEH_StackAlloc:  in isSEHInstruction()
785   case ARM::SEH_SaveRegs:  in isSEHInstruction()
786   case ARM::SEH_SaveRegs_Ret:  in isSEHInstruction()
787   case ARM::SEH_SaveSP:  in isSEHInstruction()
788   case ARM::SEH_SaveFRegs:  in isSEHInstruction()
789   case ARM::SEH_SaveLR:  in isSEHInstruction()
790   case ARM::SEH_Nop:  in isSEHInstruction()
791   case ARM::SEH_Nop_Ret:  in isSEHInstruction()
792   case ARM::SEH_PrologEnd:  in isSEHInstruction()
793   case ARM::SEH_EpilogStart:  in isSEHInstruction()
794   case ARM::SEH_EpilogEnd:  in isSEHInstruction()
814 /// instructions to materializea destreg = basereg + immediate in ARM / Thumb2
896   case ARM::t2ADDri:  in getAddSubImmediate()
899   case ARM::t2SUBri:  in getAddSubImmediate()
900   case ARM::t2SUBri12:  in getAddSubImmediate()
904   case ARM::tSUBi3:  in getAddSubImmediate()
905   case ARM::tSUBi8:  in getAddSubImmediate()