116 ARMBaseInstrInfo::ARMBaseInstrInfo(const ARMSubtarget& STI)  in ARMBaseInstrInfo()  function in ARMBaseInstrInfo
130 ARMBaseInstrInfo::CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI,  in CreateTargetHazardRecognizer()
143 ScheduleHazardRecognizer *ARMBaseInstrInfo::CreateTargetMIHazardRecognizer(  in CreateTargetMIHazardRecognizer()
165 ScheduleHazardRecognizer *ARMBaseInstrInfo::
180 ARMBaseInstrInfo::convertToThreeAddress(MachineInstr &MI, LiveVariables *LV,  in convertToThreeAddress()
356 bool ARMBaseInstrInfo::analyzeBranch(MachineBasicBlock &MBB,  in analyzeBranch()
472 unsigned ARMBaseInstrInfo::removeBranch(MachineBasicBlock &MBB,  in removeBranch()
499 unsigned ARMBaseInstrInfo::insertBranch(MachineBasicBlock &MBB,  in insertBranch()
551 bool ARMBaseInstrInfo::
561 bool ARMBaseInstrInfo::isPredicated(const MachineInstr &MI) const {  in isPredicated()
577 std::string ARMBaseInstrInfo::createMIROperandComment(  in createMIROperandComment()
602 bool ARMBaseInstrInfo::PredicateInstruction(  in PredicateInstruction()
636 bool ARMBaseInstrInfo::SubsumesPredicate(ArrayRef<MachineOperand> Pred1,  in SubsumesPredicate()
662 bool ARMBaseInstrInfo::ClobbersPredicate(MachineInstr &MI,  in ClobbersPredicate()
686 bool ARMBaseInstrInfo::isCPSRDefined(const MachineInstr &MI) {  in isCPSRDefined()
718     return !ARMBaseInstrInfo::isCPSRDefined(*MI);  in isEligibleForITBlock()
725 bool ARMBaseInstrInfo::isPredicable(const MachineInstr &MI) const {  in isPredicable()
779 unsigned ARMBaseInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {  in getInstSizeInBytes()
817 unsigned ARMBaseInstrInfo::getInstBundleLength(const MachineInstr &MI) const {  in getInstBundleLength()
828 void ARMBaseInstrInfo::copyFromCPSR(MachineBasicBlock &MBB,  in copyFromCPSR()
848 void ARMBaseInstrInfo::copyToCPSR(MachineBasicBlock &MBB,  in copyToCPSR()
892 void ARMBaseInstrInfo::copyPhysReg(MachineBasicBlock &MBB,  in copyPhysReg()
1059 ARMBaseInstrInfo::isCopyInstrImpl(const MachineInstr &MI) const {  in isCopyInstrImpl()
1075 ARMBaseInstrInfo::describeLoadedValue(const MachineInstr &MI,  in describeLoadedValue()
1105 ARMBaseInstrInfo::AddDReg(MachineInstrBuilder &MIB, unsigned Reg,  in AddDReg()
1116 void ARMBaseInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,  in storeRegToStackSlot()
1308 Register ARMBaseInstrInfo::isStoreToStackSlot(const MachineInstr &MI,  in isStoreToStackSlot()
1360 Register ARMBaseInstrInfo::isStoreToStackSlotPostFE(const MachineInstr &MI,  in isStoreToStackSlotPostFE()
1373 void ARMBaseInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,  in loadRegFromStackSlot()
1559 Register ARMBaseInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,  in isLoadFromStackSlot()
1617 Register ARMBaseInstrInfo::isLoadFromStackSlotPostFE(const MachineInstr &MI,  in isLoadFromStackSlotPostFE()
1632 void ARMBaseInstrInfo::expandMEMCPY(MachineBasicBlock::iterator MI) const {  in expandMEMCPY()
1635   const ARMBaseInstrInfo *TII = Subtarget.getInstrInfo();  in expandMEMCPY()
1686 bool ARMBaseInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {  in expandPostRAPseudo()
1809 void ARMBaseInstrInfo::reMaterialize(MachineBasicBlock &MBB,  in reMaterialize()
1837 ARMBaseInstrInfo::duplicate(MachineBasicBlock &MBB,  in duplicate()
1861 bool ARMBaseInstrInfo::produceSameValue(const MachineInstr &MI0,  in produceSameValue()
1948 bool ARMBaseInstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,  in areLoadsFromSameBasePtr()
2015 bool ARMBaseInstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,  in shouldScheduleLoadsNear()
2045 bool ARMBaseInstrInfo::isSchedulingBoundary(const MachineInstr &MI,  in isSchedulingBoundary()
2095 bool ARMBaseInstrInfo::
2121 bool ARMBaseInstrInfo::
2186 ARMBaseInstrInfo::extraSizeToPredicateInstructions(const MachineFunction &MF,  in extraSizeToPredicateInstructions()
2200 ARMBaseInstrInfo::predictBranchSizeForIfCvt(MachineInstr &MI) const {  in predictBranchSizeForIfCvt()
2223 ARMBaseInstrInfo::isProfitableToUnpredicate(MachineBasicBlock &TMBB,  in isProfitableToUnpredicate()
2256 MachineInstr *ARMBaseInstrInfo::commuteInstructionImpl(MachineInstr &MI,  in commuteInstructionImpl()
2285 ARMBaseInstrInfo::canFoldIntoMOVCC(Register Reg, const MachineRegisterInfo &MRI,  in canFoldIntoMOVCC()
2319 bool ARMBaseInstrInfo::analyzeSelect(const MachineInstr &MI,  in analyzeSelect()
2341 ARMBaseInstrInfo::optimizeSelect(MachineInstr &MI,  in optimizeSelect()
2473                                    const ARMBaseInstrInfo &TII,  in emitARMRegPlusImmediate()
2633                                 const ARMBaseInstrInfo &TII) {  in rewriteARMFrameIndex()
2788 bool ARMBaseInstrInfo::analyzeCompare(const MachineInstr &MI, Register &SrcReg,  in analyzeCompare()
3014 bool ARMBaseInstrInfo::optimizeCompareInstr(  in optimizeCompareInstr()
3294 bool ARMBaseInstrInfo::shouldSink(const MachineInstr &MI) const {  in shouldSink()
3312 bool ARMBaseInstrInfo::foldImmediate(MachineInstr &UseMI, MachineInstr &DefMI,  in foldImmediate()
3709 unsigned ARMBaseInstrInfo::getNumLDMAddresses(const MachineInstr &MI) const {  in getNumLDMAddresses()
3763 unsigned ARMBaseInstrInfo::getNumMicroOps(const InstrItineraryData *ItinData,  in getNumMicroOps()
3877 ARMBaseInstrInfo::getVLDMDefCycle(const InstrItineraryData *ItinData,  in getVLDMDefCycle()
3917 ARMBaseInstrInfo::getLDMDefCycle(const InstrItineraryData *ItinData,  in getLDMDefCycle()
3951 ARMBaseInstrInfo::getVSTMUseCycle(const InstrItineraryData *ItinData,  in getVSTMUseCycle()
3990 ARMBaseInstrInfo::getSTMUseCycle(const InstrItineraryData *ItinData,  in getSTMUseCycle()
4017 std::optional<unsigned> ARMBaseInstrInfo::getOperandLatency(  in getOperandLatency()
4363 std::optional<unsigned> ARMBaseInstrInfo::getOperandLatency(  in getOperandLatency()
4397 std::optional<unsigned> ARMBaseInstrInfo::getOperandLatencyImpl(  in getOperandLatencyImpl()
4458 ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,  in getOperandLatency()
4716 unsigned ARMBaseInstrInfo::getPredicationCost(const MachineInstr &MI) const {  in getPredicationCost()
4735 unsigned ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,  in getInstrLatency()
4786 unsigned ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,  in getInstrLatency()
4804 bool ARMBaseInstrInfo::hasHighOperandLatency(const TargetSchedModel &SchedModel,  in hasHighOperandLatency()
4825 bool ARMBaseInstrInfo::hasLowDefLatency(const TargetSchedModel &SchedModel,  in hasLowDefLatency()
4842 bool ARMBaseInstrInfo::verifyInstruction(const MachineInstr &MI,  in verifyInstruction()
4913 void ARMBaseInstrInfo::expandLoadStackGuardBase(MachineBasicBlock::iterator MI,  in expandLoadStackGuardBase()
5006 ARMBaseInstrInfo::isFpMLxInstruction(unsigned Opcode, unsigned &MulOpc,  in isFpMLxInstruction()
5042 ARMBaseInstrInfo::getExecutionDomain(const MachineInstr &MI) const {  in getExecutionDomain()
5132 void ARMBaseInstrInfo::setExecutionDomain(MachineInstr &MI,  in setExecutionDomain()
5340 unsigned ARMBaseInstrInfo::getPartialRegUpdateClearance(  in getPartialRegUpdateClearance()
5401 void ARMBaseInstrInfo::breakPartialRegDependency(  in breakPartialRegDependency()
5434 bool ARMBaseInstrInfo::hasNOP() const {  in hasNOP()
5438 bool ARMBaseInstrInfo::isSwiftFastImmShift(const MachineInstr *MI) const {  in isSwiftFastImmShift()
5452 bool ARMBaseInstrInfo::getRegSequenceLikeInputs(  in getRegSequenceLikeInputs()
5479 bool ARMBaseInstrInfo::getExtractSubregLikeInputs(  in getExtractSubregLikeInputs()
5502 bool ARMBaseInstrInfo::getInsertSubregLikeInputs(  in getInsertSubregLikeInputs()
5530 ARMBaseInstrInfo::decomposeMachineOperandsTargetFlags(unsigned TF) const {  in decomposeMachineOperandsTargetFlags()
5536 ARMBaseInstrInfo::getSerializableDirectMachineOperandTargetFlags() const {  in getSerializableDirectMachineOperandTargetFlags()
5548 ARMBaseInstrInfo::getSerializableBitmaskMachineOperandTargetFlags() const {  in getSerializableBitmaskMachineOperandTargetFlags()
5562 ARMBaseInstrInfo::isAddImmediate(const MachineInstr &MI, Register Reg) const {  in isAddImmediate()
5823 ARMBaseInstrInfo::findRegisterToSaveLRTo(outliner::Candidate &C) const {  in findRegisterToSaveLRTo()
5875 ARMBaseInstrInfo::getOutliningCandidateInfo(  in getOutliningCandidateInfo()
6094 bool ARMBaseInstrInfo::checkAndUpdateStackOffset(MachineInstr *MI,  in checkAndUpdateStackOffset()
6197 void ARMBaseInstrInfo::mergeOutliningCandidateAttributes(  in mergeOutliningCandidateAttributes()
6209 bool ARMBaseInstrInfo::isFunctionSafeToOutlineFrom(  in isFunctionSafeToOutlineFrom()
6232 bool ARMBaseInstrInfo::isMBBSafeToOutlineFrom(MachineBasicBlock &MBB,  in isMBBSafeToOutlineFrom()
6281 ARMBaseInstrInfo::getOutliningTypeImpl(MachineBasicBlock::iterator &MIT,  in getOutliningTypeImpl()
6426 void ARMBaseInstrInfo::fixupPostOutline(MachineBasicBlock &MBB) const {  in fixupPostOutline()
6432 void ARMBaseInstrInfo::saveLROnStack(MachineBasicBlock &MBB,  in saveLROnStack()
6493 void ARMBaseInstrInfo::emitCFIForLRSaveToReg(MachineBasicBlock &MBB,  in emitCFIForLRSaveToReg()
6508 void ARMBaseInstrInfo::restoreLRFromStack(MachineBasicBlock &MBB,  in restoreLRFromStack()
6569 void ARMBaseInstrInfo::emitCFIForLRRestoreFromReg(  in emitCFIForLRRestoreFromReg()
6582 void ARMBaseInstrInfo::buildOutlinedFrame(  in buildOutlinedFrame()
6658 MachineBasicBlock::iterator ARMBaseInstrInfo::insertOutlinedCall(  in insertOutlinedCall()
6722 bool ARMBaseInstrInfo::shouldOutlineFromFunctionByDefault(  in shouldOutlineFromFunctionByDefault()
6727 bool ARMBaseInstrInfo::isReallyTriviallyReMaterializable(  in isReallyTriviallyReMaterializable()
6976 ARMBaseInstrInfo::analyzeLoopForPipelining(MachineBasicBlock *LoopBB) const {  in analyzeLoopForPipelining()