Lines Matching +full:reg +full:- +full:spacing
1 //===-- ARMBaseInstrInfo.cpp - ARM Instruction Information ----------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
75 #define DEBUG_TYPE "arm-instrinfo"
81 EnableARM3Addr("enable-arm-3-addr-conv", cl::Hidden,
82 cl::desc("Enable ARM 2-addr to 3-addr conv"));
84 /// ARM_MLxEntry - Record information about MLA / MLS instructions.
134 static_cast<const ARMSubtarget *>(STI)->getInstrItineraryData(); in CreateTargetHazardRecognizer()
135 return new ScoreboardHazardRecognizer(II, DAG, "pre-RA-sched"); in CreateTargetHazardRecognizer()
141 // - pre-RA scheduling
142 // - post-RA scheduling when FeatureUseMISched is set
148 // post-RA scheduling; we can tell that we're post-RA because we don't in CreateTargetMIHazardRecognizer()
150 // Cortex-M7: TRM indicates that there is a single ITCM bank and two DTCM in CreateTargetMIHazardRecognizer()
152 if (Subtarget.isCortexM7() && !DAG->hasVRegLiveness()) in CreateTargetMIHazardRecognizer()
153 MHR->AddHazardRecognizer( in CreateTargetMIHazardRecognizer()
160 MHR->AddHazardRecognizer(std::unique_ptr<ScheduleHazardRecognizer>(BHR)); in CreateTargetMIHazardRecognizer()
164 // Called during post-RA scheduling when FeatureUseMISched is not set
171 MHR->AddHazardRecognizer(std::make_unique<ARMHazardRecognizerFPMLx>()); in CreateTargetPostRAHazardRecognizer()
175 MHR->AddHazardRecognizer(std::unique_ptr<ScheduleHazardRecognizer>(BHR)); in CreateTargetPostRAHazardRecognizer()
187 MachineFunction &MF = *MI.getParent()->getParent(); in convertToThreeAddress()
199 // Try splitting an indexed load/store to an un-indexed one plus an add/sub in convertToThreeAddress()
213 const MachineOperand &Offset = MI.getOperand(NumOps - 3); in convertToThreeAddress()
217 unsigned OffImm = MI.getOperand(NumOps - 2).getImm(); in convertToThreeAddress()
218 ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI.getOperand(NumOps - 1).getImm(); in convertToThreeAddress()
225 if (ARM_AM::getSOImmVal(Amt) == -1) in convertToThreeAddress()
259 // Immediate is 8-bits. It's guaranteed to fit in a so_imm operand. in convertToThreeAddress()
309 UpdateMI->getOperand(0).setIsDead(); in convertToThreeAddress()
318 Register Reg = MO.getReg(); in convertToThreeAddress() local
320 LiveVariables::VarInfo &VI = LV->getVarInfo(Reg); in convertToThreeAddress()
322 MachineInstr *NewMI = (Reg == WBReg) ? UpdateMI : MemMI; in convertToThreeAddress()
324 LV->addVirtualRegisterDead(Reg, *NewMI); in convertToThreeAddress()
330 if (!NewMI->readsRegister(Reg, /*TRI=*/nullptr)) in convertToThreeAddress()
332 LV->addVirtualRegisterKilled(Reg, *NewMI); in convertToThreeAddress()
367 --I; in analyzeBranch()
371 while (isPredicated(*I) || I->isTerminator() || I->isDebugValue()) { in analyzeBranch()
379 while (I->isDebugInstr() || !I->isTerminator() || in analyzeBranch()
380 isSpeculationBarrierEndBBOpcode(I->getOpcode()) || in analyzeBranch()
381 I->getOpcode() == ARM::t2DoLoopStartTP){ in analyzeBranch()
384 --I; in analyzeBranch()
387 if (isIndirectBranchOpcode(I->getOpcode()) || in analyzeBranch()
388 isJumpTableBranchOpcode(I->getOpcode())) { in analyzeBranch()
392 } else if (isUncondBranchOpcode(I->getOpcode())) { in analyzeBranch()
393 TBB = I->getOperand(0).getMBB(); in analyzeBranch()
394 } else if (isCondBranchOpcode(I->getOpcode())) { in analyzeBranch()
401 TBB = I->getOperand(0).getMBB(); in analyzeBranch()
402 Cond.push_back(I->getOperand(1)); in analyzeBranch()
403 Cond.push_back(I->getOperand(2)); in analyzeBranch()
404 } else if (I->isReturn()) { in analyzeBranch()
407 } else if (I->getOpcode() == ARM::t2LoopEnd && in analyzeBranch()
409 ->getSubtarget<ARMSubtarget>() in analyzeBranch()
414 TBB = I->getOperand(1).getMBB(); in analyzeBranch()
415 Cond.push_back(MachineOperand::CreateImm(I->getOpcode())); in analyzeBranch()
416 Cond.push_back(I->getOperand(0)); in analyzeBranch()
423 // Cleanup code - to be run for unpredicated unconditional branches and in analyzeBranch()
426 (isUncondBranchOpcode(I->getOpcode()) || in analyzeBranch()
427 isIndirectBranchOpcode(I->getOpcode()) || in analyzeBranch()
428 isJumpTableBranchOpcode(I->getOpcode()) || in analyzeBranch()
429 I->isReturn())) { in analyzeBranch()
430 // Forget any previous condition branch information - it no longer applies. in analyzeBranch()
464 --I; in analyzeBranch()
467 // We made it past the terminators without bailing out - we must have in analyzeBranch()
480 if (!isUncondBranchOpcode(I->getOpcode()) && in removeBranch()
481 !isCondBranchOpcode(I->getOpcode()) && I->getOpcode() != ARM::t2LoopEnd) in removeBranch()
485 I->eraseFromParent(); in removeBranch()
490 --I; in removeBranch()
491 if (!isCondBranchOpcode(I->getOpcode()) && I->getOpcode() != ARM::t2LoopEnd) in removeBranch()
495 I->eraseFromParent(); in removeBranch()
506 ARMFunctionInfo *AFI = MBB.getParent()->getInfo<ARMFunctionInfo>(); in insertBranch()
507 int BOpc = !AFI->isThumbFunction() in insertBranch()
508 ? ARM::B : (AFI->isThumb2Function() ? ARM::t2B : ARM::tB); in insertBranch()
509 int BccOpc = !AFI->isThumbFunction() in insertBranch()
510 ? ARM::Bcc : (AFI->isThumb2Function() ? ARM::t2Bcc : ARM::tBcc); in insertBranch()
511 bool isThumb = AFI->isThumbFunction() || AFI->isThumb2Function(); in insertBranch()
536 // Two-way conditional branch. in insertBranch()
564 MachineBasicBlock::const_instr_iterator E = MI.getParent()->instr_end(); in isPredicated()
565 while (++I != E && I->isInsideBundle()) { in isPredicated()
566 int PIdx = I->findFirstPredOperandIdx(); in isPredicated()
567 if (PIdx != -1 && I->getOperand(PIdx).getImm() != ARMCC::AL) in isPredicated()
574 return PIdx != -1 && MI.getOperand(PIdx).getImm() != ARMCC::AL; in isPredicated()
607 MachineInstrBuilder(*MI.getParent()->getParent(), MI) in PredicateInstruction()
614 if (PIdx != -1) { in PredicateInstruction()
694 switch (MI->getOpcode()) { in isEligibleForITBlock()
722 /// isPredicable - Return true if the specified instruction can be predicated.
735 const MachineFunction *MF = MI.getParent()->getParent(); in isPredicable()
737 MF->getInfo<ARMFunctionInfo>(); in isPredicable()
746 const ARMSubtarget &ST = MF->getSubtarget<ARMSubtarget>(); in isPredicable()
752 if (AFI->isThumb2Function()) { in isPredicable()
763 for (const MachineOperand &MO : MI->operands()) { in IsCPSRDead()
777 /// GetInstSize - Return the size of the specified MachineInstr.
782 const MCAsmInfo *MAI = MF->getTarget().getMCAsmInfo(); in getInstSizeInBytes()
790 // instructions are 2-4 bytes, and ARM instructions are 4 bytes), in in getInstSizeInBytes()
810 if (!MF->getInfo<ARMFunctionInfo>()->isThumbFunction()) in getInstSizeInBytes()
820 MachineBasicBlock::const_instr_iterator E = MI.getParent()->instr_end(); in getInstBundleLength()
821 while (++I != E && I->isInsideBundle()) { in getInstBundleLength()
822 assert(!I->isBundle() && "No nested bundle!"); in getInstBundleLength()
837 BuildMI(MBB, I, I->getDebugLoc(), get(Opc), DestReg); in copyFromCPSR()
840 // APSR. However, there are lots of other possibilities on M-class cores. in copyFromCPSR()
856 MachineInstrBuilder MIB = BuildMI(MBB, I, I->getDebugLoc(), get(Opc)); in copyToCPSR()
937 int Spacing = 1; in copyPhysReg() local
969 Spacing = 2; in copyPhysReg()
974 Spacing = 2; in copyPhysReg()
979 Spacing = 2; in copyPhysReg()
993 BuildMI(MBB, I, I->getDebugLoc(), get(ARM::VMSR_P0), DestReg) in copyPhysReg()
999 BuildMI(MBB, I, I->getDebugLoc(), get(ARM::VMRS_P0), DestReg) in copyPhysReg()
1005 BuildMI(MBB, I, I->getDebugLoc(), get(ARM::VMSR_FPSCR_NZCVQC), DestReg) in copyPhysReg()
1011 BuildMI(MBB, I, I->getDebugLoc(), get(ARM::VMRS_FPSCR_NZCVQC), DestReg) in copyPhysReg()
1017 assert(Opc && "Impossible reg-to-reg copy"); in copyPhysReg()
1022 // Copy register tuples backward when the first Dest reg overlaps with SrcReg. in copyPhysReg()
1023 if (TRI->regsOverlap(SrcReg, TRI->getSubReg(DestReg, BeginIdx))) { in copyPhysReg()
1024 BeginIdx = BeginIdx + ((SubRegs - 1) * Spacing); in copyPhysReg()
1025 Spacing = -Spacing; in copyPhysReg()
1031 Register Dst = TRI->getSubReg(DestReg, BeginIdx + i * Spacing); in copyPhysReg()
1032 Register Src = TRI->getSubReg(SrcReg, BeginIdx + i * Spacing); in copyPhysReg()
1033 assert(Dst && Src && "Bad sub-register"); in copyPhysReg()
1038 Mov = BuildMI(MBB, I, I->getDebugLoc(), get(Opc), Dst).addReg(Src); in copyPhysReg()
1052 // Add implicit super-register defs and kills to the last instruction. in copyPhysReg()
1053 Mov->addRegisterDefined(DestReg, TRI); in copyPhysReg()
1055 Mov->addRegisterKilled(SrcReg, TRI); in copyPhysReg()
1076 Register Reg) const { in describeLoadedValue()
1078 Register DstReg = DstSrcPair->Destination->getReg(); in describeLoadedValue()
1080 // TODO: We don't handle cases where the forwarding reg is narrower/wider in describeLoadedValue()
1090 // We also don't handle the reverse situation, where the forwarding reg is in describeLoadedValue()
1098 if (DstReg != Reg) in describeLoadedValue()
1101 return TargetInstrInfo::describeLoadedValue(MI, Reg); in describeLoadedValue()
1105 ARMBaseInstrInfo::AddDReg(MachineInstrBuilder &MIB, unsigned Reg, in AddDReg() argument
1109 return MIB.addReg(Reg, State); in AddDReg()
1111 if (Register::isPhysicalRegister(Reg)) in AddDReg()
1112 return MIB.addReg(TRI->getSubReg(Reg, SubIdx), State); in AddDReg()
1113 return MIB.addReg(Reg, State, SubIdx); in AddDReg()
1130 switch (TRI->getSpillSize(*RC)) { in storeRegToStackSlot()
1140 llvm_unreachable("Unknown reg class!"); in storeRegToStackSlot()
1165 llvm_unreachable("Unknown reg class!"); in storeRegToStackSlot()
1193 llvm_unreachable("Unknown reg class!"); in storeRegToStackSlot()
1221 llvm_unreachable("Unknown reg class!"); in storeRegToStackSlot()
1245 llvm_unreachable("Unknown reg class!"); in storeRegToStackSlot()
1254 // spilled def has a sub-register index. in storeRegToStackSlot()
1278 llvm_unreachable("Unknown reg class!"); in storeRegToStackSlot()
1301 llvm_unreachable("Unknown reg class!"); in storeRegToStackSlot()
1304 llvm_unreachable("Unknown reg class!"); in storeRegToStackSlot()
1366 cast<FixedStackPseudoSourceValue>(Accesses.front()->getPseudoValue()) in isStoreToStackSlotPostFE()
1367 ->getFrameIndex(); in isStoreToStackSlotPostFE()
1380 if (I != MBB.end()) DL = I->getDebugLoc(); in loadRegFromStackSlot()
1388 switch (TRI->getSpillSize(*RC)) { in loadRegFromStackSlot()
1397 llvm_unreachable("Unknown reg class!"); in loadRegFromStackSlot()
1419 llvm_unreachable("Unknown reg class!"); in loadRegFromStackSlot()
1451 llvm_unreachable("Unknown reg class!"); in loadRegFromStackSlot()
1475 llvm_unreachable("Unknown reg class!"); in loadRegFromStackSlot()
1498 llvm_unreachable("Unknown reg class!"); in loadRegFromStackSlot()
1528 llvm_unreachable("Unknown reg class!"); in loadRegFromStackSlot()
1552 llvm_unreachable("Unknown reg class!"); in loadRegFromStackSlot()
1623 cast<FixedStackPseudoSourceValue>(Accesses.front()->getPseudoValue()) in isLoadFromStackSlotPostFE()
1624 ->getFrameIndex(); in isLoadFromStackSlotPostFE()
1637 DebugLoc dl = MI->getDebugLoc(); in expandMEMCPY()
1638 MachineBasicBlock *BB = MI->getParent(); in expandMEMCPY()
1641 if (isThumb1 || !MI->getOperand(1).isDead()) { in expandMEMCPY()
1642 MachineOperand LDWb(MI->getOperand(1)); in expandMEMCPY()
1643 LDM = BuildMI(*BB, MI, dl, TII->get(isThumb2 ? ARM::t2LDMIA_UPD in expandMEMCPY()
1648 LDM = BuildMI(*BB, MI, dl, TII->get(isThumb2 ? ARM::t2LDMIA : ARM::LDMIA)); in expandMEMCPY()
1651 if (isThumb1 || !MI->getOperand(0).isDead()) { in expandMEMCPY()
1652 MachineOperand STWb(MI->getOperand(0)); in expandMEMCPY()
1653 STM = BuildMI(*BB, MI, dl, TII->get(isThumb2 ? ARM::t2STMIA_UPD in expandMEMCPY()
1658 STM = BuildMI(*BB, MI, dl, TII->get(isThumb2 ? ARM::t2STMIA : ARM::STMIA)); in expandMEMCPY()
1661 MachineOperand LDBase(MI->getOperand(3)); in expandMEMCPY()
1664 MachineOperand STBase(MI->getOperand(2)); in expandMEMCPY()
1670 for (MachineOperand &MO : llvm::drop_begin(MI->operands(), 5)) in expandMEMCPY()
1673 [&TRI](const unsigned &Reg1, const unsigned &Reg2) -> bool { in expandMEMCPY()
1678 for (const auto &Reg : ScratchRegs) { in expandMEMCPY() local
1679 LDM.addReg(Reg, RegState::Define); in expandMEMCPY()
1680 STM.addReg(Reg, RegState::Kill); in expandMEMCPY()
1683 BB->erase(MI); in expandMEMCPY()
1689 MI.getParent()->erase(MI); in expandPostRAPseudo()
1705 // Look for a copy between even S-registers. That is where we keep floats in expandPostRAPseudo()
1713 unsigned DstRegD = TRI->getMatchingSuperReg(DstRegS, ARM::ssub_0, in expandPostRAPseudo()
1715 unsigned SrcRegD = TRI->getMatchingSuperReg(SrcRegS, ARM::ssub_0, in expandPostRAPseudo()
1722 // sub-register insertion. in expandPostRAPseudo()
1732 MachineInstrBuilder MIB(*MI.getParent()->getParent(), MI); in expandPostRAPseudo()
1734 // Get rid of the old implicit-def of DstRegD. Leave it if it defines a Q-reg in expandPostRAPseudo()
1735 // or some other super-register. in expandPostRAPseudo()
1737 if (ImpDefIdx != -1) in expandPostRAPseudo()
1754 // sub-register. Don't kill it. Only kill the ssub_0 sub-register. in expandPostRAPseudo()
1770 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPI]; in duplicateCPV()
1776 unsigned PCLabelId = AFI->createPICLabelUId(); in duplicateCPV()
1781 // zero for non-PIC in ARM or Thumb. The callers are all of thumb LDR in duplicateCPV()
1784 if (ACPV->isGlobalValue()) in duplicateCPV()
1786 cast<ARMConstantPoolConstant>(ACPV)->getGV(), PCLabelId, ARMCP::CPValue, in duplicateCPV()
1787 4, ACPV->getModifier(), ACPV->mustAddCurrentAddress()); in duplicateCPV()
1788 else if (ACPV->isExtSymbol()) in duplicateCPV()
1791 cast<ARMConstantPoolSymbol>(ACPV)->getSymbol(), PCLabelId, 4); in duplicateCPV()
1792 else if (ACPV->isBlockAddress()) in duplicateCPV()
1794 Create(cast<ARMConstantPoolConstant>(ACPV)->getBlockAddress(), PCLabelId, in duplicateCPV()
1796 else if (ACPV->isLSDA()) in duplicateCPV()
1799 else if (ACPV->isMachineBasicBlock()) in duplicateCPV()
1802 cast<ARMConstantPoolMBB>(ACPV)->getMBB(), PCLabelId, 4); in duplicateCPV()
1805 CPI = MCP->getConstantPoolIndex(NewCPV, MCPE.getAlign()); in duplicateCPV()
1817 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(&Orig); in reMaterialize()
1818 MI->substituteRegister(Orig.getOperand(0).getReg(), DestReg, SubIdx, TRI); in reMaterialize()
1843 switch (I->getOpcode()) { in duplicate()
1847 unsigned CPI = I->getOperand(1).getIndex(); in duplicate()
1849 I->getOperand(1).setIndex(CPI); in duplicate()
1850 I->getOperand(2).setImm(PCLabelId); in duplicate()
1854 if (!I->isBundledWithSucc()) in duplicate()
1888 const MachineFunction *MF = MI0.getParent()->getParent(); in produceSameValue()
1889 const MachineConstantPool *MCP = MF->getConstantPool(); in produceSameValue()
1892 const MachineConstantPoolEntry &MCPE0 = MCP->getConstants()[CPI0]; in produceSameValue()
1893 const MachineConstantPoolEntry &MCPE1 = MCP->getConstants()[CPI1]; in produceSameValue()
1901 return ACPV0->hasSameValue(ACPV1); in produceSameValue()
1919 MachineInstr *Def0 = MRI->getVRegDef(Addr0); in produceSameValue()
1920 MachineInstr *Def1 = MRI->getVRegDef(Addr1); in produceSameValue()
1940 /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to
1946 /// FIXME: remove this in favor of the MachineInstr interface once pre-RA-sched
1954 if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode()) in areLoadsFromSameBasePtr()
1980 if (!IsLoadOpcode(Load1->getMachineOpcode()) || in areLoadsFromSameBasePtr()
1981 !IsLoadOpcode(Load2->getMachineOpcode())) in areLoadsFromSameBasePtr()
1985 if (Load1->getOperand(0) != Load2->getOperand(0) || in areLoadsFromSameBasePtr()
1986 Load1->getOperand(4) != Load2->getOperand(4)) in areLoadsFromSameBasePtr()
1990 if (Load1->getOperand(3) != Load2->getOperand(3)) in areLoadsFromSameBasePtr()
1994 if (isa<ConstantSDNode>(Load1->getOperand(1)) && in areLoadsFromSameBasePtr()
1995 isa<ConstantSDNode>(Load2->getOperand(1))) { in areLoadsFromSameBasePtr()
1996 Offset1 = cast<ConstantSDNode>(Load1->getOperand(1))->getSExtValue(); in areLoadsFromSameBasePtr()
1997 Offset2 = cast<ConstantSDNode>(Load2->getOperand(1))->getSExtValue(); in areLoadsFromSameBasePtr()
2004 /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
2013 /// FIXME: remove this in favor of the MachineInstr interface once pre-RA-sched
2023 if ((Offset2 - Offset1) / 8 > 64) in shouldScheduleLoadsNear()
2031 if ((Load1->getMachineOpcode() != Load2->getMachineOpcode()) && in shouldScheduleLoadsNear()
2032 !((Load1->getMachineOpcode() == ARM::t2LDRBi8 && in shouldScheduleLoadsNear()
2033 Load2->getMachineOpcode() == ARM::t2LDRBi12) || in shouldScheduleLoadsNear()
2034 (Load1->getMachineOpcode() == ARM::t2LDRBi12 && in shouldScheduleLoadsNear()
2035 Load2->getMachineOpcode() == ARM::t2LDRBi8))) in shouldScheduleLoadsNear()
2076 while (++I != MBB->end() && I->isDebugInstr()) in isSchedulingBoundary()
2078 if (I != MBB->end() && I->getOpcode() == ARM::t2IT) in isSchedulingBoundary()
2082 // a stack-oriented pointer, as it's unlikely to be profitable. This in isSchedulingBoundary()
2086 // Calls don't actually change the stack pointer, even if they have imp-defs. in isSchedulingBoundary()
2105 if (MBB.getParent()->getFunction().hasOptSize()) { in isProfitableToIfCvt()
2107 if (!Pred->empty()) { in isProfitableToIfCvt()
2108 MachineInstr *LastMI = &*Pred->rbegin(); in isProfitableToIfCvt()
2109 if (LastMI->getOpcode() == ARM::t2Bcc) { in isProfitableToIfCvt()
2134 if (Subtarget.isThumb2() && TBB.getParent()->getFunction().hasMinSize()) { in isProfitableToIfCvt()
2162 PredCost -= 1 * ScalingUpFactor; in isProfitableToIfCvt()
2171 PredCost += ((TCycles + FCycles - 4) / 4) * ScalingUpFactor; in isProfitableToIfCvt()
2188 // Thumb2 needs a 2-byte IT instruction to predicate up to 4 instructions. in extraSizeToPredicateInstructions()
2210 // For Thumb2, all branches are 32-bit instructions during the if conversion in predictBranchSizeForIfCvt()
2211 // pass, but may be replaced with 16-bit instructions during size reduction. in predictBranchSizeForIfCvt()
2225 // Reduce false anti-dependencies to let the target's out-of-order execution in isProfitableToUnpredicate()
2230 /// getInstrPredicate - If instruction is predicated, returns its predicate
2236 if (PIdx == -1) { in getInstrPredicate()
2274 CommutedMI->getOperand(CommutedMI->findFirstPredOperandIdx()) in commuteInstructionImpl()
2285 ARMBaseInstrInfo::canFoldIntoMOVCC(Register Reg, const MachineRegisterInfo &MRI, in canFoldIntoMOVCC() argument
2287 if (!Reg.isVirtual()) in canFoldIntoMOVCC()
2289 if (!MRI.hasOneNonDBGUse(Reg)) in canFoldIntoMOVCC()
2291 MachineInstr *MI = MRI.getVRegDef(Reg); in canFoldIntoMOVCC()
2297 // Check if MI has any non-dead defs or physreg uses. This also detects in canFoldIntoMOVCC()
2299 for (const MachineOperand &MO : llvm::drop_begin(MI->operands(), 1)) { in canFoldIntoMOVCC()
2314 if (!MI->isSafeToMove(/* AliasAnalysis = */ nullptr, DontMoveAcrossStores)) in canFoldIntoMOVCC()
2346 MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo(); in optimizeSelect()
2368 BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), DefMI->getDesc(), DestReg); in optimizeSelect()
2371 const MCInstrDesc &DefDesc = DefMI->getDesc(); in optimizeSelect()
2374 NewMI.add(DefMI->getOperand(i)); in optimizeSelect()
2383 // DefMI is not the -S version that sets CPSR, so add an optional %noreg. in optimizeSelect()
2384 if (NewMI->hasOptionalDef()) in optimizeSelect()
2393 NewMI->tieOperands(0, NewMI->getNumOperands() - 1); in optimizeSelect()
2403 if (DefMI->getParent() != MI.getParent()) in optimizeSelect()
2404 NewMI->clearKillInfo(); in optimizeSelect()
2407 DefMI->eraseFromParent(); in optimizeSelect()
2485 if (isSub) NumBytes = -NumBytes; in emitARMRegPlusImmediate()
2495 assert(ARM_AM::getSOImmVal(ThisVal) != -1 && "Bit extraction didn't work?"); in emitARMRegPlusImmediate()
2513 // micro-operations, it's only really a great benefit to code-size. in tryFoldSPUpdateIntoPushPop()
2520 bool IsPop = isPopOpcode(MI->getOpcode()); in tryFoldSPUpdateIntoPushPop()
2521 bool IsPush = isPushOpcode(MI->getOpcode()); in tryFoldSPUpdateIntoPushPop()
2525 bool IsVFPPushPop = MI->getOpcode() == ARM::VSTMDDB_UPD || in tryFoldSPUpdateIntoPushPop()
2526 MI->getOpcode() == ARM::VLDMDIA_UPD; in tryFoldSPUpdateIntoPushPop()
2527 bool IsT1PushPop = MI->getOpcode() == ARM::tPUSH || in tryFoldSPUpdateIntoPushPop()
2528 MI->getOpcode() == ARM::tPOP || in tryFoldSPUpdateIntoPushPop()
2529 MI->getOpcode() == ARM::tPOP_RET; in tryFoldSPUpdateIntoPushPop()
2531 assert((IsT1PushPop || (MI->getOperand(0).getReg() == ARM::SP && in tryFoldSPUpdateIntoPushPop()
2532 MI->getOperand(1).getReg() == ARM::SP)) && in tryFoldSPUpdateIntoPushPop()
2533 "trying to fold sp update into non-sp-updating push/pop"); in tryFoldSPUpdateIntoPushPop()
2535 // The VFP push & pop act on D-registers, so we can only fold an adjustment in tryFoldSPUpdateIntoPushPop()
2536 // by a multiple of 8 bytes in correctly. Similarly rN is 4-bytes. Don't try in tryFoldSPUpdateIntoPushPop()
2557 // re-adding them since the order matters, so save the existing ones in tryFoldSPUpdateIntoPushPop()
2563 unsigned FirstRegEnc = -1; in tryFoldSPUpdateIntoPushPop()
2566 for (int i = MI->getNumOperands() - 1; i >= RegListIdx; --i) { in tryFoldSPUpdateIntoPushPop()
2567 MachineOperand &MO = MI->getOperand(i); in tryFoldSPUpdateIntoPushPop()
2571 TRI->getEncodingValue(MO.getReg()) < FirstRegEnc) in tryFoldSPUpdateIntoPushPop()
2572 FirstRegEnc = TRI->getEncodingValue(MO.getReg()); in tryFoldSPUpdateIntoPushPop()
2575 const MCPhysReg *CSRegs = TRI->getCalleeSavedRegs(&MF); in tryFoldSPUpdateIntoPushPop()
2578 for (int CurRegEnc = FirstRegEnc - 1; CurRegEnc >= 0 && RegsNeeded; in tryFoldSPUpdateIntoPushPop()
2579 --CurRegEnc) { in tryFoldSPUpdateIntoPushPop()
2580 unsigned CurReg = RegClass->getRegister(CurRegEnc); in tryFoldSPUpdateIntoPushPop()
2581 if (IsT1PushPop && CurRegEnc > TRI->getEncodingValue(ARM::R7)) in tryFoldSPUpdateIntoPushPop()
2589 --RegsNeeded; in tryFoldSPUpdateIntoPushPop()
2596 // callee-saved. in tryFoldSPUpdateIntoPushPop()
2598 MI->getParent()->computeRegisterLiveness(TRI, CurReg, MI) != in tryFoldSPUpdateIntoPushPop()
2611 --RegsNeeded; in tryFoldSPUpdateIntoPushPop()
2620 for (int i = MI->getNumOperands() - 1; i >= RegListIdx; --i) in tryFoldSPUpdateIntoPushPop()
2621 MI->removeOperand(i); in tryFoldSPUpdateIntoPushPop()
2653 Offset = -Offset; in rewriteARMFrameIndex()
2659 if (ARM_AM::getSOImmVal(Offset) != -1) { in rewriteARMFrameIndex()
2676 assert(ARM_AM::getSOImmVal(ThisImmVal) != -1 && in rewriteARMFrameIndex()
2694 InstrOffs *= -1; in rewriteARMFrameIndex()
2701 InstrOffs *= -1; in rewriteARMFrameIndex()
2712 InstrOffs *= -1; in rewriteARMFrameIndex()
2720 InstrOffs *= -1; in rewriteARMFrameIndex()
2738 assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!"); in rewriteARMFrameIndex()
2740 Offset = -Offset; in rewriteARMFrameIndex()
2749 unsigned Mask = (1 << NumBits) - 1; in rewriteARMFrameIndex()
2758 ImmedOffset = -ImmedOffset; in rewriteARMFrameIndex()
2771 ImmedOffset = -ImmedOffset; in rewriteARMFrameIndex()
2780 Offset = (isSub) ? -Offset : Offset; in rewriteARMFrameIndex()
2784 /// analyzeCompare - For a comparison instruction, return the source registers
2821 /// isSuitableForMask - Identify a suitable 'and' instruction that
2823 /// as a 'tst' instruction. Provide a limited look-through for copies.
2827 switch (MI->getOpcode()) { in isSuitableForMask()
2830 if (CmpMask != MI->getOperand(2).getImm()) in isSuitableForMask()
2832 if (SrcReg == MI->getOperand(CommonUse ? 1 : 0).getReg()) in isSuitableForMask()
2840 /// getCmpToAddCondition - assume the flags are set by CMP(a,b), return
2853 /// isRedundantFlagInstr - check whether the first instruction, whose only
2864 if ((CmpI->getOpcode() == ARM::CMPrr || CmpI->getOpcode() == ARM::t2CMPrr) && in isRedundantFlagInstr()
2865 (OI->getOpcode() == ARM::SUBrr || OI->getOpcode() == ARM::t2SUBrr) && in isRedundantFlagInstr()
2866 ((OI->getOperand(1).getReg() == SrcReg && in isRedundantFlagInstr()
2867 OI->getOperand(2).getReg() == SrcReg2) || in isRedundantFlagInstr()
2868 (OI->getOperand(1).getReg() == SrcReg2 && in isRedundantFlagInstr()
2869 OI->getOperand(2).getReg() == SrcReg))) { in isRedundantFlagInstr()
2874 if (CmpI->getOpcode() == ARM::tCMPr && OI->getOpcode() == ARM::tSUBrr && in isRedundantFlagInstr()
2875 ((OI->getOperand(2).getReg() == SrcReg && in isRedundantFlagInstr()
2876 OI->getOperand(3).getReg() == SrcReg2) || in isRedundantFlagInstr()
2877 (OI->getOperand(2).getReg() == SrcReg2 && in isRedundantFlagInstr()
2878 OI->getOperand(3).getReg() == SrcReg))) { in isRedundantFlagInstr()
2883 if ((CmpI->getOpcode() == ARM::CMPri || CmpI->getOpcode() == ARM::t2CMPri) && in isRedundantFlagInstr()
2884 (OI->getOpcode() == ARM::SUBri || OI->getOpcode() == ARM::t2SUBri) && in isRedundantFlagInstr()
2885 OI->getOperand(1).getReg() == SrcReg && in isRedundantFlagInstr()
2886 OI->getOperand(2).getImm() == ImmValue) { in isRedundantFlagInstr()
2891 if (CmpI->getOpcode() == ARM::tCMPi8 && in isRedundantFlagInstr()
2892 (OI->getOpcode() == ARM::tSUBi8 || OI->getOpcode() == ARM::tSUBi3) && in isRedundantFlagInstr()
2893 OI->getOperand(2).getReg() == SrcReg && in isRedundantFlagInstr()
2894 OI->getOperand(3).getImm() == ImmValue) { in isRedundantFlagInstr()
2899 if ((CmpI->getOpcode() == ARM::CMPrr || CmpI->getOpcode() == ARM::t2CMPrr) && in isRedundantFlagInstr()
2900 (OI->getOpcode() == ARM::ADDrr || OI->getOpcode() == ARM::t2ADDrr || in isRedundantFlagInstr()
2901 OI->getOpcode() == ARM::ADDri || OI->getOpcode() == ARM::t2ADDri) && in isRedundantFlagInstr()
2902 OI->getOperand(0).isReg() && OI->getOperand(1).isReg() && in isRedundantFlagInstr()
2903 OI->getOperand(0).getReg() == SrcReg && in isRedundantFlagInstr()
2904 OI->getOperand(1).getReg() == SrcReg2) { in isRedundantFlagInstr()
2909 if (CmpI->getOpcode() == ARM::tCMPr && in isRedundantFlagInstr()
2910 (OI->getOpcode() == ARM::tADDi3 || OI->getOpcode() == ARM::tADDi8 || in isRedundantFlagInstr()
2911 OI->getOpcode() == ARM::tADDrr) && in isRedundantFlagInstr()
2912 OI->getOperand(0).getReg() == SrcReg && in isRedundantFlagInstr()
2913 OI->getOperand(2).getReg() == SrcReg2) { in isRedundantFlagInstr()
2922 switch (MI->getOpcode()) { in isOptimizeCompareCandidate()
3007 /// optimizeCompareInstr - Convert the instruction supplying the argument to the
3018 MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg); in optimizeCompareInstr()
3026 UI = MRI->use_instr_begin(SrcReg), UE = MRI->use_instr_end(); in optimizeCompareInstr()
3028 if (UI->getParent() != CmpInstr.getParent()) in optimizeCompareInstr()
3043 B = CmpInstr.getParent()->begin(); in optimizeCompareInstr()
3057 else if (MI->getParent() != CmpInstr.getParent() || CmpValue != 0) { in optimizeCompareInstr()
3088 --I; in optimizeCompareInstr()
3089 if (I != E && !MI->readsRegister(ARM::CPSR, TRI)) { in optimizeCompareInstr()
3091 for (; I != E; --I) { in optimizeCompareInstr()
3092 if (I->getOpcode() != ARM::tMOVi8) { in optimizeCompareInstr()
3098 MI = MI->removeFromParent(); in optimizeCompareInstr()
3100 CmpInstr.getParent()->insert(E, MI); in optimizeCompareInstr()
3111 const MachineInstr &Instr = *--I; in optimizeCompareInstr()
3131 // In some cases, we scan the use-list of an instruction for an AND; in optimizeCompareInstr()
3150 // We can't use a predicated instruction - it doesn't always write the flags. in optimizeCompareInstr()
3159 // live-out. in optimizeCompareInstr()
3164 E = CmpInstr.getParent()->end(); in optimizeCompareInstr()
3186 CC = (ARMCC::CondCodes)Instr.getOperand(IO - 1).getImm(); in optimizeCompareInstr()
3218 unsigned Opc = SubAdd->getOpcode(); in optimizeCompareInstr()
3225 (SrcReg2 != 0 && SubAdd->getOperand(OpI).getReg() == SrcReg2 && in optimizeCompareInstr()
3226 SubAdd->getOperand(OpI + 1).getReg() == SrcReg)) { in optimizeCompareInstr()
3235 std::make_pair(&((*I).getOperand(IO - 1)), NewCC)); in optimizeCompareInstr()
3264 // If CPSR is not killed nor re-defined, we should check whether it is in optimizeCompareInstr()
3265 // live-out. If it is live-out, do not optimize. in optimizeCompareInstr()
3268 for (MachineBasicBlock *Succ : MBB->successors()) in optimizeCompareInstr()
3269 if (Succ->isLiveIn(ARM::CPSR)) in optimizeCompareInstr()
3273 // Toggle the optional operand to CPSR (if it exists - in Thumb1 we always in optimizeCompareInstr()
3276 unsigned CPSRRegNum = MI->getNumExplicitOperands() - 1; in optimizeCompareInstr()
3277 MI->getOperand(CPSRRegNum).setReg(ARM::CPSR); in optimizeCompareInstr()
3278 MI->getOperand(CPSRRegNum).setIsDef(true); in optimizeCompareInstr()
3287 OperandsToUpdate[i].first->setImm(OperandsToUpdate[i].second); in optimizeCompareInstr()
3289 MI->clearRegisterDeads(ARM::CPSR); in optimizeCompareInstr()
3305 if (Next != MI.getParent()->end() && in shouldSink()
3313 Register Reg, in foldImmediate() argument
3324 if (!MRI->hasOneNonDBGUse(Reg)) in foldImmediate()
3330 const MachineOperand &MO = DefMI.getOperand(NumOps - 1); in foldImmediate()
3340 if (UseMI.getOperand(NumOps - 1).getReg() == ARM::CPSR) in foldImmediate()
3361 Commute = UseMI.getOperand(2).getReg() != Reg; in foldImmediate()
3373 else if (ARM_AM::isSOImmTwoPartVal(-ImmVal)) { in foldImmediate()
3374 ImmVal = -ImmVal; in foldImmediate()
3405 else if (ARM_AM::isT2SOImmTwoPartVal(-ImmVal)) { in foldImmediate()
3406 ImmVal = -ImmVal; in foldImmediate()
3433 const TargetRegisterClass *TRC = MRI->getRegClass(Reg); in foldImmediate()
3434 Register NewReg = MRI->createVirtualRegister(TRC); in foldImmediate()
3456 MRI->constrainRegClass(UseMI.getOperand(0).getReg(), TRC); in foldImmediate()
3466 int UOps = ItinData->getNumMicroOps(Desc.getSchedClass()); in getNumMicroOpsSwiftLdSt()
3687 // Return the number of 32-bit words loaded by LDM or stored by STM. If this
3714 Size += (*I)->getSize().getValue(); in getNumLDMAddresses()
3717 // the values can actually go up to 32 for floating-point load/store in getNumLDMAddresses()
3757 UOps += 2; // One for base reg wb, one for write to pc. in getNumMicroOpsSingleIssuePlusExtras()
3765 if (!ItinData || ItinData->isEmpty()) in getNumMicroOps()
3770 int ItinUOps = ItinData->getNumMicroOps(Class); in getNumMicroOps()
3781 llvm_unreachable("Unexpected multi-uops instruction!"); in getNumMicroOps()
3789 // On Cortex-A8, each pair of register loads / stores can be scheduled on the in getNumMicroOps()
3791 // separately by assuming the address is not 64-bit aligned. in getNumMicroOps()
3793 // On Cortex-A9, the formula is simply (#reg / 2) + (#reg % 2). If the address in getNumMicroOps()
3794 // is not 64-bit aligned, then AGU would take an extra cycle. For VFP / NEON in getNumMicroOps()
3795 // load / store multiple, the formula is (#reg / 2) + (#reg % 2) + 1. in getNumMicroOps()
3808 unsigned NumRegs = MI.getNumOperands() - Desc.getNumOperands(); in getNumMicroOps()
3844 unsigned NumRegs = MI.getNumOperands() - Desc.getNumOperands() + 1; in getNumMicroOps()
3863 // If there are odd number of registers or if it's not 64-bit aligned, in getNumMicroOps()
3866 (*MI.memoperands_begin())->getAlign() < Align(8)) in getNumMicroOps()
3880 int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1; in getVLDMDefCycle()
3883 return ItinData->getOperandCycle(DefClass, DefIdx); in getVLDMDefCycle()
3904 // If there are odd number of 'S' registers or if it's not 64-bit aligned, in getVLDMDefCycle()
3920 int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1; in getLDMDefCycle()
3923 return ItinData->getOperandCycle(DefClass, DefIdx); in getLDMDefCycle()
3936 // If there are odd number of registers or if it's not 64-bit aligned, in getLDMDefCycle()
3954 int RegNo = (int)(UseIdx+1) - UseMCID.getNumOperands() + 1; in getVSTMUseCycle()
3956 return ItinData->getOperandCycle(UseClass, UseIdx); in getVSTMUseCycle()
3977 // If there are odd number of 'S' registers or if it's not 64-bit aligned, in getVSTMUseCycle()
3993 int RegNo = (int)(UseIdx+1) - UseMCID.getNumOperands() + 1; in getSTMUseCycle()
3995 return ItinData->getOperandCycle(UseClass, UseIdx); in getSTMUseCycle()
4006 // If there are odd number of registers or if it's not 64-bit aligned, in getSTMUseCycle()
4025 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx); in getOperandLatency()
4034 DefCycle = ItinData->getOperandCycle(DefClass, DefIdx); in getOperandLatency()
4075 UseCycle = ItinData->getOperandCycle(UseClass, UseIdx); in getOperandLatency()
4113 UseCycle = *DefCycle - *UseCycle + 1; in getOperandLatency()
4118 if (ItinData->hasPipelineForwarding(DefClass, DefMCID.getNumOperands()-1, in getOperandLatency()
4120 UseCycle = *UseCycle - 1; in getOperandLatency()
4121 } else if (ItinData->hasPipelineForwarding(DefClass, DefIdx, in getOperandLatency()
4123 UseCycle = *UseCycle - 1; in getOperandLatency()
4131 const MachineInstr *MI, unsigned Reg, in getBundledDefMI() argument
4137 assert(II->isInsideBundle() && "Empty bundle?"); in getBundledDefMI()
4139 int Idx = -1; in getBundledDefMI()
4140 while (II->isInsideBundle()) { in getBundledDefMI()
4141 Idx = II->findRegisterDefOperandIdx(Reg, TRI, false, true); in getBundledDefMI()
4142 if (Idx != -1) in getBundledDefMI()
4144 --II; in getBundledDefMI()
4148 assert(Idx != -1 && "Cannot find bundled definition!"); in getBundledDefMI()
4154 const MachineInstr &MI, unsigned Reg, in getBundledUseMI() argument
4159 assert(II->isInsideBundle() && "Empty bundle?"); in getBundledUseMI()
4160 MachineBasicBlock::const_instr_iterator E = MI.getParent()->instr_end(); in getBundledUseMI()
4163 int Idx = -1; in getBundledUseMI()
4164 while (II != E && II->isInsideBundle()) { in getBundledUseMI()
4165 Idx = II->findRegisterUseOperandIdx(Reg, TRI, false); in getBundledUseMI()
4166 if (Idx != -1) in getBundledUseMI()
4168 if (II->getOpcode() != ARM::t2IT) in getBundledUseMI()
4173 if (Idx == -1) { in getBundledUseMI()
4190 // FIXME: Shifter op hack: no shift (i.e. [r +/- r]) or [r + r << 2] in adjustDefLatency()
4200 --Adjust; in adjustDefLatency()
4210 --Adjust; in adjustDefLatency()
4228 Adjust -= 2; in adjustDefLatency()
4231 --Adjust; in adjustDefLatency()
4241 Adjust -= 2; in adjustDefLatency()
4354 // If the address is not 64-bit aligned, the latencies of these in adjustDefLatency()
4367 if (!ItinData || ItinData->isEmpty()) in getOperandLatency()
4371 Register Reg = DefMO.getReg(); in getOperandLatency() local
4377 getBundledDefMI(&getRegisterInfo(), &DefMI, Reg, DefIdx, DefAdj); in getOperandLatency()
4378 if (ResolvedDefMI->isCopyLike() || ResolvedDefMI->isInsertSubreg() || in getOperandLatency()
4379 ResolvedDefMI->isRegSequence() || ResolvedDefMI->isImplicitDef()) { in getOperandLatency()
4387 getBundledUseMI(&getRegisterInfo(), UseMI, Reg, UseIdx, UseAdj); in getOperandLatency()
4393 ItinData, *ResolvedDefMI, DefIdx, ResolvedDefMI->getDesc(), DefAdj, DefMO, in getOperandLatency()
4394 Reg, *ResolvedUseMI, UseIdx, ResolvedUseMI->getDesc(), UseAdj); in getOperandLatency()
4400 const MachineOperand &DefMO, unsigned Reg, const MachineInstr &UseMI, in getOperandLatencyImpl() argument
4402 if (Reg == ARM::CPSR) { in getOperandLatencyImpl()
4404 // fpscr -> cpsr stalls over 20 cycles on A8 (and earlier?) in getOperandLatencyImpl()
4415 // For Thumb2 and -Os, prefer scheduling CPSR setting instruction close to in getOperandLatencyImpl()
4417 // incur a code size penalty (not able to use the CPSR setting 16-bit in getOperandLatencyImpl()
4420 const MachineFunction *MF = DefMI.getParent()->getParent(); in getOperandLatencyImpl()
4422 if (MF->getFunction().hasFnAttribute(Attribute::OptimizeForSize)) in getOperandLatencyImpl()
4423 --Latency; in getOperandLatencyImpl()
4432 ? (*DefMI.memoperands_begin())->getAlign().value() in getOperandLatencyImpl()
4435 ? (*UseMI.memoperands_begin())->getAlign().value() in getOperandLatencyImpl()
4448 // Adjust for dynamic def-side opcode variants not captured by the itinerary. in getOperandLatencyImpl()
4450 if (Adj >= 0 || (int)*Latency > -Adj) { in getOperandLatencyImpl()
4461 if (!DefNode->isMachineOpcode()) in getOperandLatency()
4464 const MCInstrDesc &DefMCID = get(DefNode->getMachineOpcode()); in getOperandLatency()
4469 if (!ItinData || ItinData->isEmpty()) in getOperandLatency()
4472 if (!UseNode->isMachineOpcode()) { in getOperandLatency()
4474 ItinData->getOperandCycle(DefMCID.getSchedClass(), DefIdx); in getOperandLatency()
4477 return !Latency || Latency <= (unsigned)Threshold ? 1 : *Latency - Adj; in getOperandLatency()
4480 const MCInstrDesc &UseMCID = get(UseNode->getMachineOpcode()); in getOperandLatency()
4482 unsigned DefAlign = !DefMN->memoperands_empty() in getOperandLatency()
4483 ? (*DefMN->memoperands_begin())->getAlign().value() in getOperandLatency()
4486 unsigned UseAlign = !UseMN->memoperands_empty() in getOperandLatency()
4487 ? (*UseMN->memoperands_begin())->getAlign().value() in getOperandLatency()
4497 // FIXME: Shifter op hack: no shift (i.e. [r +/- r]) or [r + r << 2] in getOperandLatency()
4503 unsigned ShOpVal = DefNode->getConstantOperandVal(2); in getOperandLatency()
4507 Latency = *Latency - 1; in getOperandLatency()
4515 unsigned ShAmt = DefNode->getConstantOperandVal(2); in getOperandLatency()
4517 Latency = *Latency - 1; in getOperandLatency()
4528 unsigned ShOpVal = DefNode->getConstantOperandVal(2); in getOperandLatency()
4533 Latency = *Latency - 2; in getOperandLatency()
4535 Latency = *Latency - 1; in getOperandLatency()
4542 // Thumb2 mode: lsl 0-3 only. in getOperandLatency()
4543 Latency = *Latency - 2; in getOperandLatency()
4707 // If the address is not 64-bit aligned, the latencies of these in getOperandLatency()
4747 MachineBasicBlock::const_instr_iterator E = MI.getParent()->instr_end(); in getInstrLatency()
4748 while (++I != E && I->isInsideBundle()) { in getInstrLatency()
4749 if (I->getOpcode() != ARM::t2IT) in getInstrLatency()
4770 if (!ItinData->isEmpty() && ItinData->getNumMicroOps(Class) < 0) in getInstrLatency()
4774 unsigned Latency = ItinData->getStageLatency(Class); in getInstrLatency()
4776 // Adjust for dynamic def-side opcode variants not captured by the itinerary. in getInstrLatency()
4778 MI.hasOneMemOperand() ? (*MI.memoperands_begin())->getAlign().value() : 0; in getInstrLatency()
4780 if (Adj >= 0 || (int)Latency > -Adj) { in getInstrLatency()
4788 if (!Node->isMachineOpcode()) in getInstrLatency()
4791 if (!ItinData || ItinData->isEmpty()) in getInstrLatency()
4794 unsigned Opcode = Node->getMachineOpcode(); in getInstrLatency()
4797 return ItinData->getStageLatency(get(Opcode).getSchedClass()); in getInstrLatency()
4829 if (!ItinData || ItinData->isEmpty()) in hasLowDefLatency()
4836 ItinData->getOperandCycle(DefClass, DefIdx); in hasLowDefLatency()
4849 // Make sure we don't generate a lo-lo mov that isn't supported. in verifyInstruction()
4852 ErrInfo = "Non-flag-setting Thumb1 mov is v6-only"; in verifyInstruction()
4862 Register Reg = MO.getReg(); in verifyInstruction() local
4863 if (Reg < ARM::R0 || Reg > ARM::R7) { in verifyInstruction()
4864 if (!(MI.getOpcode() == ARM::tPUSH && Reg == ARM::LR) && in verifyInstruction()
4865 !(MI.getOpcode() == ARM::tPOP_RET && Reg == ARM::PC)) { in verifyInstruction()
4919 MachineBasicBlock &MBB = *MI->getParent(); in expandLoadStackGuardBase()
4920 DebugLoc DL = MI->getDebugLoc(); in expandLoadStackGuardBase()
4921 Register Reg = MI->getOperand(0).getReg(); in expandLoadStackGuardBase() local
4929 BuildMI(MBB, MI, DL, get(LoadImmOpc), Reg) in expandLoadStackGuardBase()
4937 Module &M = *MBB.getParent()->getFunction().getParent(); in expandLoadStackGuardBase()
4940 // The offset won't fit in the LDR's 12-bit immediate field, so emit an in expandLoadStackGuardBase()
4944 BuildMI(MBB, MI, DL, get(AddOpc), Reg) in expandLoadStackGuardBase()
4945 .addReg(Reg, RegState::Kill) in expandLoadStackGuardBase()
4953 cast<GlobalValue>((*MI->memoperands_begin())->getValue()); in expandLoadStackGuardBase()
4960 if (GV->hasDLLImportStorageClass()) in expandLoadStackGuardBase()
4968 if (LoadImmOpc == ARM::tMOVi32imm) { // Thumb-1 execute-only in expandLoadStackGuardBase()
4971 ARMSysReg::lookupMClassSysRegByName("apsr_nzcvq")->Encoding; in expandLoadStackGuardBase()
4975 BuildMI(MBB, MI, DL, get(LoadImmOpc), Reg) in expandLoadStackGuardBase()
4982 BuildMI(MBB, MI, DL, get(LoadImmOpc), Reg) in expandLoadStackGuardBase()
4987 MIB = BuildMI(MBB, MI, DL, get(LoadOpc), Reg); in expandLoadStackGuardBase()
4988 MIB.addReg(Reg, RegState::Kill).addImm(0); in expandLoadStackGuardBase()
4992 MachineMemOperand *MMO = MBB.getParent()->getMachineMemOperand( in expandLoadStackGuardBase()
4998 MIB = BuildMI(MBB, MI, DL, get(LoadOpc), Reg); in expandLoadStackGuardBase()
4999 MIB.addReg(Reg, RegState::Kill) in expandLoadStackGuardBase()
5013 const ARM_MLxEntry &Entry = ARM_MLxTable[I->second]; in isFpMLxInstruction()
5021 //===----------------------------------------------------------------------===//
5023 //===----------------------------------------------------------------------===//
5064 // Certain instructions can go either way on Cortex-A8. in getExecutionDomain()
5077 unsigned DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_0, &ARM::DPRRegClass); in getCorrespondingDRegAndLane()
5084 DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_1, &ARM::DPRRegClass); in getCorrespondingDRegAndLane()
5086 assert(DReg && "S-register with no D super-register?"); in getCorrespondingDRegAndLane()
5090 /// getImplicitSPRUseForDPRUse - Given a use of a DPR register and lane,
5091 /// set ImplicitSReg to a register number that must be marked as implicit-use or
5092 /// zero if no register needs to be defined as implicit-use.
5102 /// If the other SPR is defined, an implicit-use of it should be added. Else,
5116 ImplicitSReg = TRI->getSubReg(DReg, in getImplicitSPRUseForDPRUse()
5119 MI.getParent()->computeRegisterLiveness(TRI, ImplicitSReg, MI); in getImplicitSPRUseForDPRUse()
5127 // implicit-use. in getImplicitSPRUseForDPRUse()
5136 MachineInstrBuilder MIB(*MI.getParent()->getParent(), MI); in setExecutionDomain()
5156 for (unsigned i = MI.getDesc().getNumOperands(); i; --i) in setExecutionDomain()
5157 MI.removeOperand(i - 1); in setExecutionDomain()
5175 for (unsigned i = MI.getDesc().getNumOperands(); i; --i) in setExecutionDomain()
5176 MI.removeOperand(i - 1); in setExecutionDomain()
5208 for (unsigned i = MI.getDesc().getNumOperands(); i; --i) in setExecutionDomain()
5209 MI.removeOperand(i - 1); in setExecutionDomain()
5243 for (unsigned i = MI.getDesc().getNumOperands(); i; --i) in setExecutionDomain()
5244 MI.removeOperand(i - 1); in setExecutionDomain()
5264 // In general there's no single instruction that can perform an S <-> S in setExecutionDomain()
5267 // the position based purely on the combination of lane-0 and lane-1 in setExecutionDomain()
5269 // vmov s0, s2 -> vext.32 d0, d0, d1, #1 vext.32 d0, d0, d0, #1 in setExecutionDomain()
5270 // vmov s1, s3 -> vext.32 d0, d1, d0, #1 vext.32 d0, d0, d0, #1 in setExecutionDomain()
5271 // vmov s0, s3 -> vext.32 d0, d0, d0, #1 vext.32 d0, d1, d0, #1 in setExecutionDomain()
5272 // vmov s1, s2 -> vext.32 d0, d0, d0, #1 vext.32 d0, d0, d1, #1 in setExecutionDomain()
5282 // <imp-use>. in setExecutionDomain()
5324 //===----------------------------------------------------------------------===//
5326 //===----------------------------------------------------------------------===//
5328 // Swift renames NEON registers with 64-bit granularity. That means any
5329 // instruction writing an S-reg implicitly reads the containing D-reg. The
5331 // on D-registers, but f32 loads are still a problem.
5335 // VLDRS - Only writes S, partial D update.
5336 // VLD1LNd32 - Writes all D-regs, explicit partial D update, 2 uops.
5337 // VLD1DUPd32 - Writes all D-regs, no partial reg update, 2 uops.
5339 // FCONSTD can be used as a dependency-breaking instruction.
5352 Register Reg = MO.getReg(); in getPartialRegUpdateClearance() local
5353 int UseOp = -1; in getPartialRegUpdateClearance()
5356 // Normal instructions writing only an S-register. in getPartialRegUpdateClearance()
5365 UseOp = MI.findRegisterUseOperandIdx(Reg, TRI, false); in getPartialRegUpdateClearance()
5376 // If this instruction actually reads a value from Reg, there is no unwanted in getPartialRegUpdateClearance()
5378 if (UseOp != -1 && MI.getOperand(UseOp).readsReg()) in getPartialRegUpdateClearance()
5381 // We must be able to clobber the whole D-reg. in getPartialRegUpdateClearance()
5382 if (Reg.isVirtual()) { in getPartialRegUpdateClearance()
5384 if (!MO.getSubReg() || MI.readsVirtualRegister(Reg)) in getPartialRegUpdateClearance()
5386 } else if (ARM::SPRRegClass.contains(Reg)) { in getPartialRegUpdateClearance()
5387 // Physical register: MI must define the full D-reg. in getPartialRegUpdateClearance()
5388 unsigned DReg = TRI->getMatchingSuperReg(Reg, ARM::ssub_0, in getPartialRegUpdateClearance()
5394 // MI has an unwanted D-register dependency. in getPartialRegUpdateClearance()
5400 // returned non-zero.
5407 Register Reg = MO.getReg(); in breakPartialRegDependency() local
5408 assert(Reg.isPhysical() && "Can't break virtual register dependencies."); in breakPartialRegDependency()
5409 unsigned DReg = Reg; in breakPartialRegDependency()
5411 // If MI defines an S-reg, find the corresponding D super-register. in breakPartialRegDependency()
5412 if (ARM::SPRRegClass.contains(Reg)) { in breakPartialRegDependency()
5413 DReg = ARM::D0 + (Reg - ARM::S0) / 2; in breakPartialRegDependency()
5414 assert(TRI->isSuperRegister(Reg, DReg) && "Register enums broken"); in breakPartialRegDependency()
5417 assert(ARM::DPRRegClass.contains(DReg) && "Can only break D-reg deps"); in breakPartialRegDependency()
5418 assert(MI.definesRegister(DReg, TRI) && "MI doesn't clobber full D-reg"); in breakPartialRegDependency()
5421 // the full D-register by loading the same value to both lanes. The in breakPartialRegDependency()
5422 // instruction is micro-coded with 2 uops, so don't do this until we can in breakPartialRegDependency()
5423 // properly schedule micro-coded instructions. The dispatcher stalls cause in breakPartialRegDependency()
5426 // Insert the dependency-breaking FCONSTD before MI. in breakPartialRegDependency()
5439 if (MI->getNumOperands() < 4) in isSwiftFastImmShift()
5441 unsigned ShOpVal = MI->getOperand(3).getImm(); in isSwiftFastImmShift()
5466 if (!MOReg->isUndef()) in getRegSequenceLikeInputs()
5467 InputRegs.push_back(RegSubRegPairAndIdx(MOReg->getReg(), in getRegSequenceLikeInputs()
5468 MOReg->getSubReg(), ARM::ssub_0)); in getRegSequenceLikeInputs()
5471 if (!MOReg->isUndef()) in getRegSequenceLikeInputs()
5472 InputRegs.push_back(RegSubRegPairAndIdx(MOReg->getReg(), in getRegSequenceLikeInputs()
5473 MOReg->getSubReg(), ARM::ssub_1)); in getRegSequenceLikeInputs()
5494 InputReg.Reg = MOReg.getReg(); in getExtractSubregLikeInputs()
5518 BaseReg.Reg = MOBaseReg.getReg(); in getInsertSubregLikeInputs()
5521 InsertedReg.Reg = MOInsertedReg.getReg(); in getInsertSubregLikeInputs()
5540 {MO_LO16, "arm-lo16"}, {MO_HI16, "arm-hi16"}, in getSerializableDirectMachineOperandTargetFlags()
5541 {MO_LO_0_7, "arm-lo-0-7"}, {MO_HI_0_7, "arm-hi-0-7"}, in getSerializableDirectMachineOperandTargetFlags()
5542 {MO_LO_8_15, "arm-lo-8-15"}, {MO_HI_8_15, "arm-hi-8-15"}, in getSerializableDirectMachineOperandTargetFlags()
5552 {MO_COFFSTUB, "arm-coffstub"}, in getSerializableBitmaskMachineOperandTargetFlags()
5553 {MO_GOT, "arm-got"}, in getSerializableBitmaskMachineOperandTargetFlags()
5554 {MO_SBREL, "arm-sbrel"}, in getSerializableBitmaskMachineOperandTargetFlags()
5555 {MO_DLLIMPORT, "arm-dllimport"}, in getSerializableBitmaskMachineOperandTargetFlags()
5556 {MO_SECREL, "arm-secrel"}, in getSerializableBitmaskMachineOperandTargetFlags()
5557 {MO_NONLAZY, "arm-nonlazy"}}; in getSerializableBitmaskMachineOperandTargetFlags()
5562 ARMBaseInstrInfo::isAddImmediate(const MachineInstr &MI, Register Reg) const { in isAddImmediate()
5567 // TODO: Handle cases where Reg is a super- or sub-register of the in isAddImmediate()
5570 if (!Op0.isReg() || Reg != Op0.getReg()) in isAddImmediate()
5575 Sign = -1; in isAddImmediate()
5589 bool llvm::registerDefinedBetween(unsigned Reg, in registerDefinedBetween() argument
5594 if (I->modifiesRegister(Reg, TRI)) in registerDefinedBetween()
5605 while (CmpMI != Br->getParent()->begin()) { in findCMPToFoldIntoCBZ()
5606 --CmpMI; in findCMPToFoldIntoCBZ()
5607 if (CmpMI->modifiesRegister(ARM::CPSR, TRI)) in findCMPToFoldIntoCBZ()
5609 if (CmpMI->readsRegister(ARM::CPSR, TRI)) in findCMPToFoldIntoCBZ()
5613 // Check that this inst is a CMP r[0-7], #0 and that the register in findCMPToFoldIntoCBZ()
5615 if (CmpMI->getOpcode() != ARM::tCMPi8 && CmpMI->getOpcode() != ARM::t2CMPri) in findCMPToFoldIntoCBZ()
5617 Register Reg = CmpMI->getOperand(0).getReg(); in findCMPToFoldIntoCBZ() local
5620 if (Pred != ARMCC::AL || CmpMI->getOperand(1).getImm() != 0) in findCMPToFoldIntoCBZ()
5622 if (!isARMLowRegister(Reg)) in findCMPToFoldIntoCBZ()
5624 if (registerDefinedBetween(Reg, CmpMI->getNextNode(), Br, TRI)) in findCMPToFoldIntoCBZ()
5633 if (Subtarget->isThumb()) { in ConstantMaterializationCost()
5636 if (Subtarget->hasV6T2Ops() && (Val <= 0xffff || // MOV in ConstantMaterializationCost()
5637 ARM_AM::getT2SOImmVal(Val) != -1 || // MOVW in ConstantMaterializationCost()
5638 ARM_AM::getT2SOImmVal(~Val) != -1)) // MVN in ConstantMaterializationCost()
5647 if (ARM_AM::getSOImmVal(Val) != -1) // MOV in ConstantMaterializationCost()
5649 if (ARM_AM::getSOImmVal(~Val) != -1) // MVN in ConstantMaterializationCost()
5651 if (Subtarget->hasV6T2Ops() && Val <= 0xffff) // MOVW in ConstantMaterializationCost()
5658 if (Subtarget->useMovt()) // MOVW + MOVT in ConstantMaterializationCost()
5689 /// I2 --> B OUTLINED_FUNCTION I1
5693 /// +-------------------------+--------+-----+
5695 /// +-------------------------+--------+-----+
5699 /// +-------------------------+--------+-----+
5703 /// called with a BL instruction, and the outlined function tail-calls the
5709 /// I2 --> BL OUTLINED_FUNCTION I1
5713 /// +-------------------------+--------+-----+
5715 /// +-------------------------+--------+-----+
5719 /// +-------------------------+--------+-----+
5728 /// I2 --> BL OUTLINED_FUNCTION I1
5733 /// +-------------------------+--------+-----+
5735 /// +-------------------------+--------+-----+
5739 /// +-------------------------+--------+-----+
5749 /// I2 --> BL OUTLINED_FUNCTION I1
5754 /// +-------------------------+--------+-----+
5756 /// +-------------------------+--------+-----+
5760 /// +-------------------------+--------+-----+
5768 /// I2 --> BL OUTLINED_FUNCTION I1
5773 /// +-------------------------+--------+-----+
5775 /// +-------------------------+--------+-----+
5779 /// +-------------------------+--------+-----+
5825 const TargetRegisterInfo &TRI = *MF->getSubtarget().getRegisterInfo(); in findRegisterToSaveLRTo()
5829 BitVector regsReserved = ARI->getReservedRegs(*MF); in findRegisterToSaveLRTo()
5832 for (Register Reg : ARM::rGPRRegClass) { in findRegisterToSaveLRTo() local
5833 if (!(Reg < regsReserved.size() && regsReserved.test(Reg)) && in findRegisterToSaveLRTo()
5834 Reg != ARM::LR && // LR is not reserved, but don't use it. in findRegisterToSaveLRTo()
5835 Reg != ARM::R12 && // R12 is not guaranteed to be preserved. in findRegisterToSaveLRTo()
5836 C.isAvailableAcrossAndOutOfSeq(Reg, TRI) && in findRegisterToSaveLRTo()
5837 C.isAvailableInsideSeq(Reg, TRI)) in findRegisterToSaveLRTo()
5838 return Reg; in findRegisterToSaveLRTo()
5924 // possible combinations of PAC-RET and BTI is going to yield one big subset in getOutliningCandidateInfo()
5926 // candidates separately for PAC-RET and BTI. in getOutliningCandidateInfo()
5930 // number prefer the non-BTI ones for outlining, since they have less in getOutliningCandidateInfo()
5934 const ARMFunctionInfo &AFI = *C.getMF()->getInfo<ARMFunctionInfo>(); in getOutliningCandidateInfo()
5946 // Likewise, partition the candidates according to PAC-RET enablement. in getOutliningCandidateInfo()
5949 const ARMFunctionInfo &AFI = *C.getMF()->getInfo<ARMFunctionInfo>(); in getOutliningCandidateInfo()
5978 *RepeatedSequenceLocs.front().getMF()->getInfo<ARMFunctionInfo>(); in getOutliningCandidateInfo()
6021 const auto Last = C.getMBB()->rbegin(); in getOutliningCandidateInfo()
6023 C.getMBB()->isReturnBlock() && !Last->isCall() in getOutliningCandidateInfo()
6097 int SPIdx = MI->findRegisterUseOperandIdx(ARM::SP, /*TRI=*/nullptr); in checkAndUpdateStackOffset()
6098 unsigned AddrMode = (MI->getDesc().TSFlags & ARMII::AddrModeMask); in checkAndUpdateStackOffset()
6114 AddrMode == ARMII::AddrModeT2_i7 || // v8.1-M MVE in checkAndUpdateStackOffset()
6115 AddrMode == ARMII::AddrModeT2_i7s2 || // v8.1-M MVE in checkAndUpdateStackOffset()
6116 AddrMode == ARMII::AddrModeT2_i7s4 || // v8.1-M sys regs VLDR/VSTR in checkAndUpdateStackOffset()
6122 unsigned NumOps = MI->getDesc().getNumOperands(); in checkAndUpdateStackOffset()
6123 unsigned ImmIdx = NumOps - 3; in checkAndUpdateStackOffset()
6125 const MachineOperand &Offset = MI->getOperand(ImmIdx); in checkAndUpdateStackOffset()
6173 case ARMII::AddrModeT1_s: // SP-relative LD/ST in checkAndUpdateStackOffset()
6182 assert(((OffVal * Scale + Fixup) & (Scale - 1)) == 0 && in checkAndUpdateStackOffset()
6186 unsigned Mask = (1 << NumBits) - 1; in checkAndUpdateStackOffset()
6190 MI->getOperand(ImmIdx).setImm(OffVal); in checkAndUpdateStackOffset()
6200 // branch-target-enforcement is guaranteed to be consistent between all in mergeOutliningCandidateAttributes()
6202 const Function &CFn = C.getMF()->getFunction(); in mergeOutliningCandidateAttributes()
6203 if (CFn.hasFnAttribute("branch-target-enforcement")) in mergeOutliningCandidateAttributes()
6204 F.addFnAttr(CFn.getFnAttribute("branch-target-enforcement")); in mergeOutliningCandidateAttributes()
6225 if (MF.getInfo<ARMFunctionInfo>()->isThumb1OnlyFunction()) in isFunctionSafeToOutlineFrom()
6236 assert(MBB.getParent()->getRegInfo().tracksLiveness() && in isMBBSafeToOutlineFrom()
6334 (Callee->getName() == "\01__gnu_mcount_nc" || in getOutliningTypeImpl()
6335 Callee->getName() == "\01mcount" || Callee->getName() == "__mcount")) in getOutliningTypeImpl()
6340 // as a tail-call. Explicitly list the call instructions we know about so in getOutliningTypeImpl()
6341 // we don't get unexpected results with call pseudo-instructions. in getOutliningTypeImpl()
6353 MachineFunction *MF = MI.getParent()->getParent(); in getOutliningTypeImpl()
6354 MachineFunction *CalleeMF = MF->getMMI().getMachineFunction(*Callee); in getOutliningTypeImpl()
6363 MachineFrameInfo &MFI = CalleeMF->getFrameInfo(); in getOutliningTypeImpl()
6385 // authentication - we insert sign and authentication instructions only if in getOutliningTypeImpl()
6447 .addImm(-Align) in saveLROnStack()
6455 .addImm(-Align) in saveLROnStack()
6474 int LROffset = Auth ? Align - 4 : Align; in saveLROnStack()
6476 unsigned DwarfLR = MRI->getDwarfRegNum(ARM::LR, true); in saveLROnStack()
6478 MCCFIInstruction::createOffset(nullptr, DwarfLR, -LROffset)); in saveLROnStack()
6484 unsigned DwarfRAC = MRI->getDwarfRegNum(ARM::RA_AUTH_CODE, true); in saveLROnStack()
6486 MCCFIInstruction::createOffset(nullptr, DwarfRAC, -Align)); in saveLROnStack()
6495 Register Reg) const { in emitCFIForLRSaveToReg()
6498 unsigned DwarfLR = MRI->getDwarfRegNum(ARM::LR, true); in emitCFIForLRSaveToReg()
6499 unsigned DwarfReg = MRI->getDwarfRegNum(Reg, true); in emitCFIForLRSaveToReg()
6541 unsigned DwarfLR = MRI->getDwarfRegNum(ARM::LR, true); in restoreLRFromStack()
6556 unsigned DwarfRAC = MRI->getDwarfRegNum(ARM::RA_AUTH_CODE, true); in restoreLRFromStack()
6573 unsigned DwarfLR = MRI->getDwarfRegNum(ARM::LR, true); in emitCFIForLRRestoreFromReg()
6586 // tail-call. in buildOutlinedFrame()
6588 MachineInstr *Call = &*--MBB.instr_end(); in buildOutlinedFrame()
6591 unsigned Opc = Call->getOperand(FuncOp).isReg() in buildOutlinedFrame()
6597 .add(Call->getOperand(FuncOp)); in buildOutlinedFrame()
6598 if (isThumb && !Call->getOperand(FuncOp).isReg()) in buildOutlinedFrame()
6600 Call->eraseFromParent(); in buildOutlinedFrame()
6624 ->getInfo<ARMFunctionInfo>() in buildOutlinedFrame()
6625 ->shouldSignReturnAddress(true); in buildOutlinedFrame()
6694 const ARMFunctionInfo &AFI = *C.getMF()->getInfo<ARMFunctionInfo>(); in insertOutlinedCall()
6697 Register Reg = findRegisterToSaveLRTo(C); in insertOutlinedCall() local
6698 assert(Reg != 0 && "No callee-saved register available?"); in insertOutlinedCall()
6701 copyPhysReg(MBB, It, DebugLoc(), Reg, ARM::LR, true); in insertOutlinedCall()
6703 emitCFIForLRSaveToReg(MBB, It, Reg); in insertOutlinedCall()
6705 copyPhysReg(MBB, It, DebugLoc(), ARM::LR, Reg, true); in insertOutlinedCall()
6708 It--; in insertOutlinedCall()
6718 It--; in insertOutlinedCall()
6758 // Bitset[0 .. MAX_STAGES-1] ... iterations needed
6781 MF(EndLoop->getParent()->getParent()), in ARMPipelinerLoopInfo()
6782 TII(MF->getSubtarget().getInstrInfo()) {} in ARMPipelinerLoopInfo()
6800 if (isCondBranchOpcode(EndLoop->getOpcode())) { in createTripCountGreaterCondition()
6801 Cond.push_back(EndLoop->getOperand(1)); in createTripCountGreaterCondition()
6802 Cond.push_back(EndLoop->getOperand(2)); in createTripCountGreaterCondition()
6803 if (EndLoop->getOperand(0).getMBB() == EndLoop->getParent()) { in createTripCountGreaterCondition()
6804 TII->reverseBranchCondition(Cond); in createTripCountGreaterCondition()
6807 } else if (EndLoop->getOpcode() == ARM::t2LoopEnd) { in createTripCountGreaterCondition()
6816 BuildMI(&MBB, LoopDec->getDebugLoc(), TII->get(ARM::t2CMPri)) in createTripCountGreaterCondition()
6817 .addReg(LoopDec->getOperand(0).getReg()) in createTripCountGreaterCondition()
6839 int Cnt = N.second.count() - N.second[SEEN_AS_LIVE] * 2; in bumpCrossIterationPressure()
6846 int Cnt = N.second.count() - N.second[SEEN_AS_LIVE] * 2; in bumpCrossIterationPressure()
6857 // Determine which values will be loop-carried after the schedule is in tooMuchRegisterPressure()
6864 if (MI->isPHI() && S.getKind() == SDep::Anti) { in tooMuchRegisterPressure()
6865 Register Reg = S.getReg(); in tooMuchRegisterPressure() local
6866 if (Reg.isVirtual()) in tooMuchRegisterPressure()
6867 CrossIterationNeeds.insert(std::make_pair(Reg.id(), IterNeed())) in tooMuchRegisterPressure()
6868 .first->second.set(0); in tooMuchRegisterPressure()
6872 Register Reg = S.getReg(); in tooMuchRegisterPressure() local
6873 if (Reg.isVirtual()) in tooMuchRegisterPressure()
6874 CrossIterationNeeds.insert(std::make_pair(Reg.id(), IterNeed())) in tooMuchRegisterPressure()
6875 .first->second |= ((1 << (OStg - Stg)) - 1); in tooMuchRegisterPressure()
6880 // Determine more-or-less what the proposed schedule (reversed) is going to in tooMuchRegisterPressure()
6881 // be; it might not be quite the same because the within-cycle ordering in tooMuchRegisterPressure()
6885 for (int Cycle = SMS.getFinalCycle(); Cycle >= SMS.getFirstCycle(); --Cycle) in tooMuchRegisterPressure()
6891 [](SUnit *A, SUnit *B) { return A->NodeNum > B->NodeNum; }); in tooMuchRegisterPressure()
6896 // Learn whether the last use/def of each cross-iteration register is a use or in tooMuchRegisterPressure()
6900 for (ConstMIBundleOperands OperI(*SU->getInstr()); OperI.isValid(); in tooMuchRegisterPressure()
6905 Register Reg = MO.getReg(); in tooMuchRegisterPressure() local
6906 auto CIter = CrossIterationNeeds.find(Reg.id()); in tooMuchRegisterPressure()
6907 if (CIter == CrossIterationNeeds.end() || CIter->second[LAST_IS_USE] || in tooMuchRegisterPressure()
6908 CIter->second[SEEN_AS_LIVE]) in tooMuchRegisterPressure()
6911 CIter->second.set(SEEN_AS_LIVE); in tooMuchRegisterPressure()
6913 CIter->second.set(LAST_IS_USE); in tooMuchRegisterPressure()
6922 RPTracker.init(MF, &RegClassInfo, nullptr, EndLoop->getParent(), in tooMuchRegisterPressure()
6923 EndLoop->getParent()->end(), false, false); in tooMuchRegisterPressure()
6924 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo(); in tooMuchRegisterPressure()
6929 MachineBasicBlock::const_iterator CurInstI = SU->getInstr(); in tooMuchRegisterPressure()
6933 // Track what cross-iteration registers would be seen as live in tooMuchRegisterPressure()
6938 Register Reg = MO.getReg(); in tooMuchRegisterPressure() local
6940 auto CIter = CrossIterationNeeds.find(Reg.id()); in tooMuchRegisterPressure()
6942 CIter->second.reset(0); in tooMuchRegisterPressure()
6943 CIter->second.reset(SEEN_AS_LIVE); in tooMuchRegisterPressure()
6947 for (auto &S : SU->Preds) { in tooMuchRegisterPressure()
6950 Register Reg = S.getReg(); in tooMuchRegisterPressure() local
6951 auto CIter = CrossIterationNeeds.find(Reg.id()); in tooMuchRegisterPressure()
6955 if (Stg - Stg2 < MAX_STAGES) in tooMuchRegisterPressure()
6956 CIter->second.set(Stg - Stg2); in tooMuchRegisterPressure()
6957 CIter->second.set(SEEN_AS_LIVE); in tooMuchRegisterPressure()
6967 if (P[I] > TRI->getRegPressureSetLimit(*MF, I)) { in tooMuchRegisterPressure()
6977 MachineBasicBlock::iterator I = LoopBB->getFirstTerminator(); in analyzeLoopForPipelining()
6978 MachineBasicBlock *Preheader = *LoopBB->pred_begin(); in analyzeLoopForPipelining()
6980 Preheader = *std::next(LoopBB->pred_begin()); in analyzeLoopForPipelining()
6982 if (I != LoopBB->end() && I->getOpcode() == ARM::t2Bcc) { in analyzeLoopForPipelining()
6985 // it can be marked as non-pipelineable, allowing the pipeliner to force in analyzeLoopForPipelining()
6988 for (auto &L : LoopBB->instrs()) { in analyzeLoopForPipelining()
7009 if (I != LoopBB->end() && I->getOpcode() == ARM::t2LoopEnd) { in analyzeLoopForPipelining()
7010 for (auto &L : LoopBB->instrs()) in analyzeLoopForPipelining()
7015 Register LoopDecResult = I->getOperand(0).getReg(); in analyzeLoopForPipelining()
7016 MachineRegisterInfo &MRI = LoopBB->getParent()->getRegInfo(); in analyzeLoopForPipelining()
7018 if (!LoopDec || LoopDec->getOpcode() != ARM::t2LoopDec) in analyzeLoopForPipelining()
7021 for (auto &J : Preheader->instrs()) in analyzeLoopForPipelining()