Lines Matching +full:0 +full:x1ff
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
55 (Bytes[0] << 16) | (Bytes[1] << 24) | (Bytes[2] << 0) | (Bytes[3] << 8); in readInstruction32()
62 Insn = ((uint64_t)Bytes[0] << 16) | ((uint64_t)Bytes[1] << 24) | in readInstruction64()
63 ((uint64_t)Bytes[2] << 0) | ((uint64_t)Bytes[3] << 8) | in readInstruction64()
72 Insn = ((uint64_t)Bytes[0] << 0) | ((uint64_t)Bytes[1] << 8) | in readInstruction48()
81 Insn = (Bytes[0] << 0) | (Bytes[1] << 8); in readInstruction16()
87 DecodeSignedOperand(MCInst &Inst, unsigned InsnS, uint64_t Address = 0,
92 DecodeFromCyclicRange(MCInst &Inst, unsigned InsnS, uint64_t Address = 0,
166 return fieldFromInstruction(Insn, 0, 6); in decodeAField()
172 unsigned S9 = Insn & 0x1ff; in DecodeMEMrs9()
173 unsigned R = (Insn & (0x7fff & ~0x1ff)) >> 9; in DecodeMEMrs9()
184 Inst, Value, Address, true, 0, AtLeast, 0)); in DecodeSymbolicOperand()
201 static_assert(B > 0, "field is empty"); in DecodeBranchTargetS()
211 static_assert(B > 0, "field is empty"); in DecodeSignedOperand()
222 static_assert(B > 0, "field is empty"); in DecodeFromCyclicRange()
242 Inst.addOperand(MCOperand::createImm(0)); in DecodeStLImmInstruction()
260 Inst.addOperand(MCOperand::createImm(0)); in DecodeLdLImmInstruction()
287 (fieldFromInstruction(Insn, 0, 2) << 3); in DecodeMoveHRegInstruction()
301 if (MCDisassembler::Success != DecodeRegisterOrImm(G, 0)) in DecodeMoveHRegInstruction()
317 Field CCField = fieldFromInstruction(Insn, 0, 4); in DecodeCCRU6Instruction()
340 Field Upper = fieldFromInstruction(Insn, 0, 5); in DecodeSOPwithRS12()
353 Size = 0; in getInstruction()
356 uint8_t DecodeByte = (Bytes[1] & 0xF7) >> 3; in getInstruction()
357 // 0x00 -> 0x07 are 32-bit instructions. in getInstruction()
358 // 0x08 -> 0x1F are 16-bit instructions. in getInstruction()
359 if (DecodeByte < 0x08) { in getInstruction()
363 Size = 0; in getInstruction()