Lines Matching +refs:cc +refs:with
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
151 // Generate many variants of a single instruction with a single defining
170 // 2 register with unsigned 6-bit immediate variant.
182 (ins immU6:$U6, ccond:$cc, GPR32:$B),
183 !strconcat(opasm, ".$cc\t$A, $B, $U6"),
190 (ins immU6:$U6, ccond:$cc, GPR32:$B),
191 !strconcat(opasm, ".$cc.f\t$A, $B, $U6"),
198 // 2 register with 32-bit immediate variant.
211 // 2 matched-register with signed 12-bit immediate variant (add r0, r0, -1).
273 // NOTE: This could be specialized later with a custom `PrintMethod` for
393 def cmov : PatFrag<(ops node:$op1, node:$op2, node:$cc),
394 (ARCcmov $op1, $op2, $cc)>;
398 (outs GPR32:$B), (ins GPR32:$C, GPR32:$B2, CCOp:$cc),
399 "mov.$cc\t$B, $C",
400 [(set GPR32:$B, (cmov i32:$C, i32:$B2, timm:$cc))]>;
403 (outs GPR32:$B), (ins u6:$C, CCOp:$cc, GPR32:$B2),
404 "mov.$cc\t$B, $C", []>;
407 (outs GPR32:$B), (ins u6:$C, CCOp:$cc, GPR32:$B2),
408 "mov.$cc.f\t$B, $C", []> {
434 def Bcc : F32_BR0_COND<(outs), (ins btargetS21:$S21, ccond:$cc),
435 "b$cc\t$S21", []>;
439 (ins btargetS9:$S9, GPR32:$B, GPR32:$C, brccond:$cc),
440 "br$cc\t$B, $C, $S9", 0, []>;
442 (ins btargetS9:$S9, GPR32:$B, immU6:$C, brccond:$cc),
443 "br$cc\t$B, $C, $S9", 1, []>;
450 (ins btarget:$T, GPR32:$B, GPR32:$C, ccond:$cc),
451 "pbr$cc\t$B, $C, $T",
452 [(ARCbrcc bb:$T, i32:$B, i32:$C, imm32:$cc)]>
456 (ins btarget:$T, GPR32:$B, i32imm:$C, ccond:$cc),
457 "pbr$cc\t$B, $C, $T",
458 [(ARCbrcc bb:$T, i32:$B, immU6:$C, imm32:$cc)]>
667 // Branch on Compare Register with Zero.
791 // Compact Load/Store instructions with offset.