1 //===- ARCInstrInfo.cpp - ARC Instruction Information -----------*- C++ -*-===//
9 // This file contains the ARC implementation of the TargetInstrInfo class.
14 #include "ARC.h"
29 #define DEBUG_TYPE "arc-inst-info"
47     : ARCGenInstrInfo(ARC::ADJCALLSTACKDOWN, ARC::ADJCALLSTACKUP), RI(ST) {}  in ARCInstrInfo()
54   return Opcode == ARC::LD_rs9 || Opcode == ARC::LDH_rs9 ||  in isLoad()
55          Opcode == ARC::LDB_rs9;  in isLoad()
59   return Opcode == ARC::ST_rs9 || Opcode == ARC::STH_rs9 ||  in isStore()
60          Opcode == ARC::STB_rs9;  in isStore()
137 static bool isUncondBranchOpcode(int Opc) { return Opc == ARC::BR; }  in isUncondBranchOpcode()
140   return Opc == ARC::BRcc_rr_p || Opc == ARC::BRcc_ru6_p;  in isCondBranchOpcode()
143 static bool isJumpOpcode(int Opc) { return Opc == ARC::J; }  in isJumpOpcode()
285   assert(ARC::GPR32RegClass.contains(SrcReg) &&  in copyPhysReg()
287   assert(ARC::GPR32RegClass.contains(DestReg) &&  in copyPhysReg()
289   BuildMI(MBB, I, DL, get(ARC::MOV_rr), DestReg)  in copyPhysReg()
309   assert(ARC::GPR32RegClass.hasSubClassEq(RC) &&  in storeRegToStackSlot()
313   BuildMI(MBB, I, DL, get(ARC::ST_rs9))  in storeRegToStackSlot()
337   assert(ARC::GPR32RegClass.hasSubClassEq(RC) &&  in loadRegFromStackSlot()
341   BuildMI(MBB, I, DL, get(ARC::LD_rs9))  in loadRegFromStackSlot()
351   assert((Cond.size() == 3) && "Invalid ARC branch condition!");  in reverseBranchCondition()
362     return BuildMI(MBB, MI, DL, get(ARC::MOV_rs12), Reg)  in loadImmediate()
366   llvm_unreachable("Need Arc long immediate instructions.");  in loadImmediate()
379          "ARC branch conditions have two components!");  in insertBranch()
382     BuildMI(&MBB, DL, get(ARC::BR)).addMBB(TBB);  in insertBranch()
385   int BccOpc = Cond[1].isImm() ? ARC::BRcc_ru6_p : ARC::BRcc_rr_p;  in insertBranch()
398   BuildMI(&MBB, DL, get(ARC::BR)).addMBB(FBB);  in insertBranch()