Lines Matching +full:6 +full:b
24 def immU6 : immU<6>;
31 // e.g. s3 field may encode the signed integers values -1 .. 6
43 let MIOperandInfo = (ops GPR32:$B, immS<9>:$S9);
49 let MIOperandInfo = (ops GPR32:$B, i32imm:$LImm);
82 def ByteSM : DataSizeMode<0b01, "B", "b">;
139 // [ABC] - 32-bit register operand. These are 6-bit fields. This encodes the
146 // B - Inst[14-12] = B[5-3], Inst[26-24] = B[2-0], when the format has B.
147 // B is always a register.
148 // C - Inst[11-6] = C[5-0], when the format has C. C can either be a register,
149 // or a 6-bit unsigned immediate (immU6), depending on the format.
171 let Inst{15-6} = S21{20-11};
180 let Inst{15-6} = S25{20-11};
191 // |26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|9|8|7|6|5|4|3|2|1|0 |
199 // |26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|9|8|7|6|5|4|3|2|1|0 |
207 // |26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|9|8|7|6|5|4|3|2|1|0|
217 // |26|25|24|23|22|21|20|19|18|17|16|15 |14|13|12|11|10|9|8|7|6|5|4|3|2|1|0|
218 // |B[2-0] |S9[7-1] | 1|S9[8]|B[5-3] |C |N|u|0|cc |
224 bits<6> B;
225 bits<6> C;
230 let Inst{26-24} = B{2-0};
234 let Inst{14-12} = B{5-3};
235 let Inst{11-6} = C;
245 // |26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|9|8|7|6|5|4|3|2|1|0|
246 // |B[2-0] | 0| 0| 1| 0| 1| 1| 1| 1| F|B[5-3] |C |subop |
247 class F32_SOP_RR<bits<5> major, bits<6> subop, bit F, dag outs, dag ins,
251 bits<6> C;
252 bits<6> B;
255 let Inst{26-24} = B{2-0};
259 let Inst{14-12} = B{5-3};
260 let Inst{11-6} = C;
268 // |26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|9|8|7|6|5|4|3|2|1|0|
269 // |B[2-0] | 0| 0| subop| F|B[5-3] |C |A |
270 class F32_DOP_RR<bits<5> major, bits<6> subop, bit F, dag outs, dag ins,
273 bits<6> C;
274 bits<6> B;
275 bits<6> A;
278 let Inst{26-24} = B{2-0};
282 let Inst{14-12} = B{5-3};
283 let Inst{11-6} = C;
287 // Conditional Dual Operand instruction. This instruction uses B as the
288 // first 2 operands (i.e, add.cc B, B, C).
289 // |26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|9|8|7|6|5|4|3|2|1|0|
290 // |B[2-0] | 1| 1| subop| F|B[5-3] |C |A |
291 class F32_DOP_CC_RR<bits<5> major, bits<6> subop, bit F, dag outs, dag ins,
295 bits<6> C;
296 bits<6> B;
299 let Inst{26-24} = B{2-0};
303 let Inst{14-12} = B{5-3};
304 let Inst{11-6} = C;
310 // 2-register, unsigned 6-bit immediate Dual Operand instruction.
311 // |26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|9|8|7|6|5|4|3|2|1|0|
312 // |B[2-0] | 0| 1| subop| F|B[5-3] |U6 |A |
313 class F32_DOP_RU6<bits<5> major, bits<6> subop, bit F, dag outs, dag ins,
316 bits<6> U6;
317 bits<6> B;
318 bits<6> A;
321 let Inst{26-24} = B{2-0};
325 let Inst{14-12} = B{5-3};
326 let Inst{11-6} = U6;
330 // 1-register, unsigned 6-bit, immediate Dual Operand instruction with
332 // |26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|9|8|7|6|5|4|3|2|1|0|
333 // |B[2-0] | 1| 1| subop| F|B[5-3] |U6 |1|cc |
334 class F32_DOP_CC_RU6<bits<5> major, bits<6> subop, bit F, dag outs, dag ins,
339 bits<6> U6;
340 bits<6> B;
343 let Inst{26-24} = B{2-0};
347 let Inst{14-12} = B{5-3};
348 let Inst{11-6} = U6;
355 // 2-register, unsigned 6-bit immediate Dual Operand instruction with
356 // condition code. This instruction uses B as the first 2 operands
357 // (i.e, add.cc B, B, u6).
358 // |26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|9|8|7|6|5|4|3|2|1|0|
359 // |B[2-0] | 1| 1| subop| F|B[5-3] |U6 |1|cc |
360 class F32_DOP_CC_RRU6<bits<5> major, bits<6> subop, bit F, dag outs, dag ins,
364 bits<6> U6;
365 bits<6> B;
368 let Inst{26-24} = B{2-0};
372 let Inst{14-12} = B{5-3};
373 let Inst{11-6} = U6;
379 // This instruction uses B as the first 2 operands (i.e., add B, B, -128).
380 // |26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|9|8|7|6|5|4|3|2|1|0|
381 // |B[2-0] | 1| 0| subop| F|B[5-3] |S12[5-0] |S12[11-6] |
382 class F32_DOP_RS12<bits<5> major, bits<6> subop, bit F, dag outs, dag ins,
385 bits<6> B;
389 let Inst{26-24} = B{2-0};
393 let Inst{14-12} = B{5-3};
394 let Inst{11-6} = S12{5-0};
395 let Inst{5-0} = S12{11-6};
399 // This instruction uses B as the first operand (i.e., lr B, [%count0]).
400 // |26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|9|8|7|6|5|4|3|2|1|0|
401 // |B[2-0] | 1| 0| subop| F|B[5-3] |S12[5-0] |S12[11-6] |
402 class F32_SOP_RS12<bits<5> major, bits<6> subop, bit F, dag outs, dag ins,
405 bits<6> B;
409 let Inst{26-24} = B{2-0};
413 let Inst{14-12} = B{5-3};
414 let Inst{11-6} = S12{5-0};
415 let Inst{5-0} = S12{11-6};
420 // 1-register, unsigned 6-bit immediate Dual Operand instruction.
421 // This instruction uses B as the first operand.
422 // |26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|9|8|7|6|5|4|3|2|1|0|
423 // |B[2-0] | 0| 1| subop| F|B[5-3] |U6 |0|0|0|0|0|0|
424 class F32_SOP_RU6<bits<5> major, bits<6> subop, bit F, dag outs, dag ins,
427 bits<6> B;
428 bits<6> U6;
431 let Inst{26-24} = B{2-0};
435 let Inst{14-12} = B{5-3};
436 let Inst{11-6} = U6;
445 class F32_DOP_RLIMM<bits<5> major, bits<6> subop, bit F, dag outs, dag ins,
448 bits<6> B;
449 bits<6> A;
454 let Inst{26-24} = B{2-0};
458 let Inst{14-12} = B{5-3};
459 let Inst{11-6} = 0b111110;
479 // Register + S9 Load. (B + S9)
480 // |26|25|24|23|22|21|20|19|18|17|16|15 |14|13|12|11|10|9|8|7|6|5|4|3|2|1|0|
481 // |B[2-0] |S9[7-0] |S9[8]|B[5-3] |di|aa |zz |x|A |
485 bits<6> B;
486 bits<6> A;
490 let Inst{26-24} = B{2-0};
493 let Inst{14-12} = B{5-3};
497 let Inst{6} = x;
508 let B = addr{14-9};
516 // |26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|9|8|7|6|5|4|3|2|1|0|
521 bits<6> LImmReg = 0b111110;
522 bits<6> A;
533 let Inst{6} = x;
541 // |26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|9|8|7|6|5|4|3|2|1|0|
542 // |B[2-0] |aa | 1| 1| 0|zz | x|di|B[5-3] | 1| 1|1|1|1|0|A |
546 bits<6> LImmReg = 0b111110;
548 bits<6> B;
549 bits<6> A;
551 let B = addr{37-32};
556 let Inst{26-24} = B{2-0};
562 let Inst{14-12} = B{5-3};
563 let Inst{11-6} = LImmReg;
570 // Register + S9 Store. (B + S9)
571 // |26|25|24|23|22|21|20|19|18|17|16|15 |14|13|12|11|10|9|8|7|6|5 |4|3|2|1|0|
572 // |B[2-0] |S9[7-0] |S9[8]|B[5-3] |C |di|aa |zz |0|
576 bits<6> B;
577 bits<6> C;
581 let Inst{26-24} = B{2-0};
584 let Inst{14-12} = B{5-3};
585 let Inst{11-6} = C;
599 let B = addr{14-9};
606 // |26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|9|8|7|6|5 |4|3|2|1|0|
611 bits<6> LImmReg = 0b111110;
612 bits<6> C;
620 let Inst{11-6} = C;
631 // |10|9|8|7|6|5|4|3|2|1|0|
649 bits<3> b;
651 let Inst{10-8} = b;
655 F16_LD_ADD_SUB<(outs GPR32:$a), (ins GPR32:$b, GPR32:$c),
668 F16_LD_ADD_SUB<(outs GPR32:$r), (ins GPR32:$b, immU<6>:$u6),
669 "add_s\t$r, $b, $u6"> {
672 bits<6> u6;
675 let Inst{6-4} = u6{5-3};
700 F16_LD_ST_1<(outs GPR32:$b), (ins immU<7>:$u7),
701 "ldi_s\t$b, [$u7]"> {
703 bits<3> b;
706 let Inst{10-8} = b;
707 let Inst{7-4} = u7{6-3};
726 InstARC<2, (outs GPR32:$a), (ins GPR32:$b, GPR32:$c),
730 bits<3> b;
734 let Inst{10-8} = b;
749 // |10|9|8|7|6|5|4|3|2|1|0|
750 // |b |c |i |u |
752 InstARC<2, (outs GPR32:$c), (ins GPR32:$b, immU<3>:$u3),
753 !strconcat(asmstr, "\t$c, $b, $u3"), []> {
755 bits<3> b;
760 let Inst{10-8} = b;
767 // |10|9|8|7|6|5|4|3|2|1|0|
768 // |b/s |h |i |H |
795 let Size = 6;
802 bits<3> b;
805 let Inst{10-8} = b;
811 F16_GEN_DOP_BASE<i, (outs GPR32:$b), (ins GPR32:$c),
812 !strconcat(asmstr, "\t$b, $b, $c")>;
815 F16_GEN_DOP_BASE<i, (outs), (ins GPR32:$b, GPR32:$c),
816 !strconcat(asmstr, "\t$b, $c")>;
819 F16_GEN_DOP_BASE<i, (outs GPR32:$b), (ins GPR32:$c),
820 !strconcat(asmstr, "\t$b, $c")>;
829 F16_GEN_SOP_BASE<i, (outs), (ins GPR32:$b), asmstr>;
834 let b = i;
839 InstARC<2, outs, ins, !strconcat(asmstr, "\t$c, [$b, $off]"), []> {
841 bits<3> b;
844 let Inst{10-8} = b;
852 let Inst{4-0} = off{6-2};
859 bits<6> off;
872 // |10|9|8|7|6|5|4|3|2|1|0|
873 // |b |i |u |
875 InstARC<2, (outs), (ins GPR32:$b, immU<5>:$u5), asmstr, []> {
877 bits<3> b;
881 let Inst{10-8} = b;
887 F16_SH_SUB_BIT<i, !strconcat(asmstr, "\t$b, $b, $u5")>;
890 // |10|9|8|7|6|5|4|3|2|1|0|
891 // |b |i |u |
913 let fieldU = u7{6-2};
917 class F16_SP_OPS_bconst<bits<3> b, string asmop> :
922 let fieldB = b;
953 bits<3> b;
955 let Inst{10-8} = b;
959 F16_OP_IMM<0b11100, (outs GPR32:$b), (ins immU<7>:$u7), asmstr> {
963 let Inst{6-0} = u7;
1002 InstARC<2, (outs), (ins GPR32:$b, btargetS8:$s8),
1003 !strconcat(asmstr, "\t$b, 0, $s8"), []> {
1005 bits<3> b;
1009 let Inst{10-8} = b;
1011 let Inst{6-0} = s8{7-1};
1037 let Inst{8-6} = i;
1038 let Inst{5-0} = s{6-1};