Lines Matching +full:22 +full:c

148 // C - Inst[11-6] = C[5-0], when the format has C.  C can either be a register,
191 // |26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|9|8|7|6|5|4|3|2|1|0   |
199 // |26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|9|8|7|6|5|4|3|2|1|0   |
207 // |26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|9|8|7|6|5|4|3|2|1|0|
217 // |26|25|24|23|22|21|20|19|18|17|16|15   |14|13|12|11|10|9|8|7|6|5|4|3|2|1|0|
218 // |B[2-0]  |S9[7-1]             | 1|S9[8]|B[5-3]  |C            |N|u|0|cc   |
225   bits<6> C;
235   let Inst{11-6} = C;
245 // |26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|9|8|7|6|5|4|3|2|1|0|
246 // |B[2-0]  | 0| 0| 1| 0| 1| 1| 1| 1| F|B[5-3]  |C            |subop      |
251   bits<6> C;
256   let Inst{23-22} = 0b00;
260   let Inst{11-6} = C;
268 // |26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|9|8|7|6|5|4|3|2|1|0|
269 // |B[2-0]  | 0| 0|            subop| F|B[5-3]  |C            |A          |
273   bits<6> C;
279   let Inst{23-22} = 0b00;
283   let Inst{11-6} = C;
288 // first 2 operands (i.e, add.cc B, B, C).
289 // |26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|9|8|7|6|5|4|3|2|1|0|
290 // |B[2-0]  | 1| 1|            subop| F|B[5-3]  |C            |A          |
295   bits<6> C;
300   let Inst{23-22} = 0b11;
304   let Inst{11-6} = C;
311 // |26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|9|8|7|6|5|4|3|2|1|0|
322   let Inst{23-22} = 0b01;
332 // |26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|9|8|7|6|5|4|3|2|1|0|
344   let Inst{23-22} = 0b11;
358 // |26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|9|8|7|6|5|4|3|2|1|0|
369   let Inst{23-22} = 0b11;
380 // |26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|9|8|7|6|5|4|3|2|1|0|
390   let Inst{23-22} = 0b10;
400 // |26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|9|8|7|6|5|4|3|2|1|0|
410   let Inst{23-22} = 0b10;
422 // |26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|9|8|7|6|5|4|3|2|1|0|
432   let Inst{23-22} = 0b01;
444 // 62 in the C register operand slot, but is otherwise F32_DOP_RR.
455   let Inst{23-22} = 0b00;
480 // |26|25|24|23|22|21|20|19|18|17|16|15   |14|13|12|11|10|9|8|7|6|5|4|3|2|1|0|
516 // |26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|9|8|7|6|5|4|3|2|1|0|
541 // |26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|9|8|7|6|5|4|3|2|1|0|
557   let Inst{23-22} = aa;
571 // |26|25|24|23|22|21|20|19|18|17|16|15   |14|13|12|11|10|9|8|7|6|5 |4|3|2|1|0|
572 // |B[2-0]  |S9[7-0]                |S9[8]|B[5-3]  |C            |di|aa |zz |0|
577   bits<6> C;
585   let Inst{11-6} = C;
606 // |26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|9|8|7|6|5 |4|3|2|1|0|
607 // | 1| 1| 0| 0                        | 1| 1| 1|C            |di|0|0|zz |0|
612   bits<6> C;
620   let Inst{11-6} = C;
655   F16_LD_ADD_SUB<(outs GPR32:$a), (ins GPR32:$b, GPR32:$c),
659   bits<3> c;
661   let Inst{7-5} = c;
726   InstARC<2, (outs GPR32:$a), (ins GPR32:$b, GPR32:$c),
731   bits<3> c;
735   let Inst{7-5} = c;
750 // |b     |c    |i  |u    |
752   InstARC<2, (outs GPR32:$c), (ins GPR32:$b, immU<3>:$u3),
753   !strconcat(asmstr, "\t$c, $b, $u3"), []> {
756   bits<3> c;
761   let Inst{7-5} = c;
803   bits<3> c;
806   let Inst{7-5} = c;
811   F16_GEN_DOP_BASE<i, (outs GPR32:$b), (ins GPR32:$c),
812   !strconcat(asmstr, "\t$b, $b, $c")>;
815   F16_GEN_DOP_BASE<i, (outs), (ins GPR32:$b, GPR32:$c),
816   !strconcat(asmstr, "\t$b, $c")>;
819   F16_GEN_DOP_BASE<i, (outs GPR32:$b), (ins GPR32:$c),
820   !strconcat(asmstr, "\t$b, $c")>;
825   let c = i;
839   InstARC<2, outs, ins, !strconcat(asmstr, "\t$c, [$b, $off]"), []> {
842   bits<3> c;
845   let Inst{7-5} = c;