Lines Matching +full:11 +full:i
148 // C - Inst[11-6] = C[5-0], when the format has C. C can either be a register,
171 let Inst{15-6} = S21{20-11};
180 let Inst{15-6} = S25{20-11};
191 // |26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|9|8|7|6|5|4|3|2|1|0 |
192 // |S25[10-1] | 1|S25[20-11] |N|0|S25[24-21]|
199 // |26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|9|8|7|6|5|4|3|2|1|0 |
200 // |S25[10-2] | 1| 0|S25[20-11] |N|0|S25[24-21]|
207 // |26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|9|8|7|6|5|4|3|2|1|0|
208 // |S25[10-2] | 0| 0|S25[20-11] |N|0|cc |
217 // |26|25|24|23|22|21|20|19|18|17|16|15 |14|13|12|11|10|9|8|7|6|5|4|3|2|1|0|
235 let Inst{11-6} = C;
245 // |26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|9|8|7|6|5|4|3|2|1|0|
260 let Inst{11-6} = C;
268 // |26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|9|8|7|6|5|4|3|2|1|0|
283 let Inst{11-6} = C;
288 // first 2 operands (i.e, add.cc B, B, C).
289 // |26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|9|8|7|6|5|4|3|2|1|0|
304 let Inst{11-6} = C;
311 // |26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|9|8|7|6|5|4|3|2|1|0|
326 let Inst{11-6} = U6;
332 // |26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|9|8|7|6|5|4|3|2|1|0|
348 let Inst{11-6} = U6;
357 // (i.e, add.cc B, B, u6).
358 // |26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|9|8|7|6|5|4|3|2|1|0|
373 let Inst{11-6} = U6;
379 // This instruction uses B as the first 2 operands (i.e., add B, B, -128).
380 // |26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|9|8|7|6|5|4|3|2|1|0|
381 // |B[2-0] | 1| 0| subop| F|B[5-3] |S12[5-0] |S12[11-6] |
394 let Inst{11-6} = S12{5-0};
395 let Inst{5-0} = S12{11-6};
399 // This instruction uses B as the first operand (i.e., lr B, [%count0]).
400 // |26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|9|8|7|6|5|4|3|2|1|0|
401 // |B[2-0] | 1| 0| subop| F|B[5-3] |S12[5-0] |S12[11-6] |
414 let Inst{11-6} = S12{5-0};
415 let Inst{5-0} = S12{11-6};
422 // |26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|9|8|7|6|5|4|3|2|1|0|
436 let Inst{11-6} = U6;
459 let Inst{11-6} = 0b111110;
480 // |26|25|24|23|22|21|20|19|18|17|16|15 |14|13|12|11|10|9|8|7|6|5|4|3|2|1|0|
494 let Inst{11} = di;
516 // |26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|9|8|7|6|5|4|3|2|1|0|
530 let Inst{11} = di;
541 // |26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|9|8|7|6|5|4|3|2|1|0|
563 let Inst{11-6} = LImmReg;
571 // |26|25|24|23|22|21|20|19|18|17|16|15 |14|13|12|11|10|9|8|7|6|5 |4|3|2|1|0|
585 let Inst{11-6} = C;
606 // |26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|9|8|7|6|5 |4|3|2|1|0|
620 let Inst{11-6} = C;
632 // | |h | |i|H |
633 class F16_COMPACT<bits<1> i, dag outs, dag ins,
639 let Inst{15-11} = 0b01000;
641 let Inst{2} = i;
650 let Inst{15-11} = 0b01001;
654 class F16_LD_SUB<bit i, string asmstr> :
662 let Inst{4} = i;
684 let Inst{15-11} = 0b01010;
687 class F16_LD_ST_s11<bit i, string asmstr> :
688 F16_LD_ST_1<(outs), (ins immS<11>:$s11), asmstr> {
690 bits<11> s11;
693 let Inst{4} = i;
713 class F16_JLI_EI<bit i, string asmstr> :
719 let Inst{15-11} = 0b01011;
720 let Inst{10} = i;
725 class F16_LD_ADD_RR<bits<2> i, string asmstr> :
733 let Inst{15-11} = 0b01100;
736 let Inst{4-3} = i;
741 class F16_GP_LD_ADD<bits<2> i, dag ins, string asmstr> :
744 let Inst{15-11} = 0b11001;
745 let Inst{10-9} = i;
750 // |b |c |i |u |
751 class F16_ADD_IMM<bits<2> i, string asmstr> :
759 let Inst{15-11} = 0b01101;
762 let Inst{4-3} = i;
768 // |b/s |h |i |H |
769 class F16_OP_HREG<bits<3> i, dag outs, dag ins, string asmstr> :
775 let Inst{15-11} = 0b01110;
778 let Inst{4-2} = i;
782 class F16_OP_HREG30<bits<3> i, dag outs, dag ins, string asmstr> :
783 F16_OP_HREG<i, outs, ins, asmstr> {
790 class F16_OP_HREG_LIMM<bits<3> i, dag outs, dag ins, string asmstr> :
791 F16_OP_HREG30<i, outs, ins, asmstr> {
799 class F16_GEN_DOP_BASE<bits<5> i, dag outs, dag ins, string asmstr> :
804 let Inst{15-11} = 0b01111;
807 let Inst{4-0} = i;
810 class F16_GEN_DOP<bits<5> i, string asmstr> :
811 F16_GEN_DOP_BASE<i, (outs GPR32:$b), (ins GPR32:$c),
814 class F16_GEN_DOP_NODST<bits<5> i, string asmstr> :
815 F16_GEN_DOP_BASE<i, (outs), (ins GPR32:$b, GPR32:$c),
818 class F16_GEN_DOP_SINGLESRC<bits<5> i, string asmstr> :
819 F16_GEN_DOP_BASE<i, (outs GPR32:$b), (ins GPR32:$c),
822 class F16_GEN_SOP_BASE<bits<3> i, dag outs, dag ins, string asmstr> :
825 let c = i;
828 class F16_GEN_SOP<bits<3> i, string asmstr> :
829 F16_GEN_SOP_BASE<i, (outs), (ins GPR32:$b), asmstr>;
831 class F16_GEN_ZOP<bits<3> i, string asmstr> :
834 let b = i;
843 let Inst{15-11} = opc;
873 // |b |i |u |
874 class F16_SH_SUB_BIT<bits<3> i, string asmstr> :
880 let Inst{15-11} = 0b10111;
882 let Inst{7-5} = i;
886 class F16_SH_SUB_BIT_DST<bits<3> i, string asmstr> :
887 F16_SH_SUB_BIT<i, !strconcat(asmstr, "\t$b, $b, $u5")>;
891 // |b |i |u |
892 class F16_SP_OPS<bits<3> i,
899 let Inst{15-11} = 0b11000;
901 let Inst{7-5} = i;
905 class F16_SP_OPS_u7_aligned<bits<3> i,
907 F16_SP_OPS<i, outs, ins, asmstr> {
925 class F16_SP_OPS_uconst<bits<3> i,
927 F16_SP_OPS_u7_aligned<i, outs, ins,
933 class F16_SP_OPS_buconst<bits<3> i, string asmop> :
934 F16_SP_OPS_u7_aligned<i, (outs), (ins),
941 class F16_SP_LD<bits<3> i, string asmop> : F16_SP_OPS_u7_aligned<i,
945 class F16_SP_ST<bits<3> i, string asmop> : F16_SP_OPS_u7_aligned<i,
954 let Inst{15-11} = opc;
958 class F16_OP_U7<bit i, string asmstr> :
962 let Inst{7} = i;
1001 class F16_BCC_REG<bit i, string asmstr> :
1008 let Inst{15-11} = 0b11101;
1010 let Inst{7} = i;
1016 class F16_BCC<bits<2> i, dag ins, string asmstr> :
1019 let Inst{15-11} = 0b11110;
1020 let Inst{10-9} = i;
1023 class F16_BCC_s10<bits<2> i, string asmstr> :
1024 F16_BCC<i, (ins btargetS10:$s),
1032 class F16_BCC_s7<bits<3> i, string asmstr> :
1037 let Inst{8-6} = i;