Lines Matching +full:10 +full:- +full:bit
1 //===-- VOPInstructions.td - Vector Instruction Definitions ---------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 bit TRANS;
12 bit ReadsModeReg;
13 bit mayRaiseFPException;
14 bit isCommutable;
15 bit isConvertibleToThreeAddress;
16 bit isMoveImm;
17 bit isReMaterializable;
18 bit isAsCheapAsAMove;
19 bit FPDPRounding;
20 bit IsInvalidSingleUseConsumer;
21 bit IsInvalidSingleUseProducer;
44 bit CanBeVOPDX = !le(VOPDOp, VOPDX_Max_Index);
69 bit IsTrue16 = P.IsTrue16;
70 bit IsInvalidSingleUseConsumer = P.IsInvalidSingleUseConsumer;
71 bit IsInvalidSingleUseProducer = P.IsInvalidSingleUseProducer;
78 list<dag> pattern = [], bit HasMods = 0> :
85 let AddedComplexity = -1000;
97 // need a post-isel hook to insert copies in order to avoid
103 bit isVOP3P = 0, bit isVop3OpSel = 0> :
126 // need a post-isel hook to insert copies in order to avoid
134 let AddedComplexity = -1000;
165 bit IsSingle = ps.Pfl.IsSingle;
166 bit IsInvalidSingleUseConsumer = ps.Pfl.IsInvalidSingleUseConsumer;
167 bit IsInvalidSingleUseProducer = ps.Pfl.IsInvalidSingleUseProducer;
209 // XXX - Is there any reason to distinguish this from regular VOP3
236 let Inst{10} = !if(P.HasSrc2Mods, src2_modifiers{1}, 0);
238 let Inst{31-26} = 0x34; //encoding
239 let Inst{40-32} = !if(P.HasSrc0, src0, 0);
240 let Inst{49-41} = !if(P.HasSrc1, src1, 0);
241 let Inst{58-50} = !if(P.HasSrc2, src2, 0);
242 let Inst{60-59} = !if(P.HasOMod, omod, 0);
250 let Inst{25-17} = op;
253 class VOP3a_gfx10<bits<10> op, VOPProfile p> : VOP3a<p> {
255 let Inst{25-16} = op;
256 let Inst{31-26} = 0x35;
259 class VOP3a_gfx11_gfx12<bits<10> op, VOPProfile p> : VOP3a_gfx10<op, p>;
261 class VOP3a_vi <bits<10> op, VOPProfile P> : VOP3a<P> {
262 let Inst{25-16} = op;
268 let Inst{7-0} = !if(p.EmitDst, vdst{7-0}, 0);
271 class VOP3e_gfx10<bits<10> op, VOPProfile p> : VOP3a_gfx10<op, p> {
273 let Inst{7-0} = !if(p.EmitDst, vdst{7-0}, 0);
276 class VOP3e_gfx11_gfx12<bits<10> op, VOPProfile p> : VOP3e_gfx10<op, p>;
278 class VOP3e_vi <bits<10> op, VOPProfile P> : VOP3a_vi <op, P> {
280 let Inst{7-0} = !if(P.EmitDst, vdst{7-0}, 0);
283 class VOP3OpSel_gfx9 <bits<10> op, VOPProfile P> : VOP3e_vi <op, P> {
290 class VOP3OpSel_gfx10<bits<10> op, VOPProfile p> : VOP3e_gfx10<op, p> {
297 class VOP3OpSel_gfx11_gfx12<bits<10> op, VOPProfile p> : VOP3OpSel_gfx10<op, p>;
299 class VOP3FP8OpSel_src_bytesel_gfx11_gfx12<bits<10> op, VOPProfile p> : VOP3e_gfx10<op, p> {
301 let Inst{11-12} = byte_sel; // NB: bit order is intentionally reversed!
302 let Inst{14-13} = 0; // op_sel2/3
305 class VOP3FP8OpSel_dst_bytesel_gfx11_gfx12<bits<10> op, VOPProfile p> : VOP3e_gfx10<op, p> {
310 let Inst{14-13} = byte_sel; // op_sel2/3
313 class VOP3DotOpSel_gfx11_gfx12<bits<10> op, VOPProfile p> : VOP3OpSel_gfx11_gfx12<op, p>{
319 class VOP3Interp_vi <bits<10> op, VOPProfile P> : VOP3e_vi <op, P> {
330 let Inst{37-32} = attr;
331 let Inst{39-38} = attrchan;
334 let Inst{49-41} = src0;
337 class VOP3Interp_gfx10<bits<10> op, VOPProfile p> : VOP3e_gfx10<op, p> {
344 let Inst{37-32} = attr;
345 let Inst{39-38} = attrchan;
347 let Inst{49-41} = src0;
352 class VOP3Interp_gfx11<bits<10> op, VOPProfile p> : VOP3Interp_gfx10<op, p>;
365 let Inst{7-0} = vdst;
366 let Inst{14-8} = sdst;
367 let Inst{31-26} = 0x34; //encoding
368 let Inst{40-32} = !if(P.HasSrc0, src0, 0);
369 let Inst{49-41} = !if(P.HasSrc1, src1, 0);
370 let Inst{58-50} = !if(P.HasSrc2, src2, 0);
371 let Inst{60-59} = !if(P.HasOMod, omod, 0);
389 let Inst{7-0} = vdst;
392 let Inst{10} = !if(P.HasSrc2Mods, src2_modifiers{1}, 0); // neg_hi src2
402 let Inst{22-16} = op;
403 let Inst{31-23} = 0x1a7; //encoding
404 let Inst{40-32} = !if(P.HasSrc0, src0, 0);
405 let Inst{49-41} = !if(P.HasSrc1, src1, 0);
406 let Inst{58-50} = !if(P.HasSrc2, src2, 0);
414 class VOP3Pe_MAI <bits<7> op, VOPProfile P, bit acc_cd = 0> : Enc64 {
416 bits<10> src0;
417 bits<10> src1;
423 let Inst{7-0} = vdst;
425 let Inst{10-8} = !if(P.HasSrc1, cbsz, 0);
426 let Inst{14-11} = !if(P.HasSrc1, abid, 0);
430 let Inst{22-16} = op;
431 let Inst{31-23} = 0x1a7; //encoding
432 let Inst{40-32} = !if(P.HasSrc0, src0{8-0}, 0);
433 let Inst{49-41} = !if(P.HasSrc1, src1{8-0}, 0);
434 let Inst{58-50} = !if(P.HasSrc2, src2, 0);
439 let Inst{63-61} = !if(P.HasSrc1, blgp, 0);
443 bits<10> vdst; // VGPR or AGPR, but not SGPR. vdst{8} is not encoded in the instruction.
444 bits<10> src0;
445 bits<10> src1;
453 let Inst{7-0} = vdst{7-0};
455 let Inst{10-8} = cbsz;
456 let Inst{14-11} = abid;
460 let Inst{22-16} = op;
461 let Inst{31-23} = 0x1a7; // encoding
462 let Inst{40-32} = src0{8-0};
463 let Inst{49-41} = src1{8-0};
464 let Inst{58-50} = idx;
469 let Inst{63-61} = blgp;
473 let Inst{31-23} = 0x198; //encoding
479 let Inst{25-17} = op;
482 class VOP3be_gfx10<bits<10> op, VOPProfile p> : VOP3be<p> {
485 let Inst{25-16} = op;
486 let Inst{31-26} = 0x35;
489 class VOP3be_gfx11_gfx12<bits<10> op, VOPProfile p> : VOP3be_gfx10<op, p>;
491 class VOP3be_vi <bits<10> op, VOPProfile P> : VOP3be<P> {
493 let Inst{25-16} = op;
523 let Inst{39-32} = !if(P.HasSrc0, src0{7-0}, 0);
524 let Inst{42-40} = !if(P.EmitDstSel, dst_sel{2-0}, ?);
525 let Inst{44-43} = !if(P.EmitDstSel, dst_unused{1-0}, ?);
527 let Inst{50-48} = !if(P.HasSrc0, src0_sel{2-0}, 0);
529 let Inst{53-52} = !if(P.HasSrc0FloatMods, src0_modifiers{1-0}, 0);
530 let Inst{58-56} = !if(P.HasSrc1, src1_sel{2-0}, 0);
532 let Inst{61-60} = !if(P.HasSrc1FloatMods, src1_modifiers{1-0}, 0);
550 bits<9> src0; // {src0_sgpr{0}, src0{7-0}}
557 let Inst{39-32} = !if(P.HasSrc0, src0{7-0}, 0);
558 let Inst{50-48} = !if(P.HasSrc0, src0_sel{2-0}, 0);
560 let Inst{53-52} = !if(P.HasSrc0FloatMods, src0_modifiers{1-0}, 0);
562 let Inst{58-56} = !if(P.HasSrc1, src1_sel{2-0}, 0);
564 let Inst{61-60} = !if(P.HasSrc1FloatMods, src1_modifiers{1-0}, 0);
565 let Inst{63} = 0; // src1_sgpr - should be specified in subclass
568 // gfx9 SDWA-A
575 let Inst{42-40} = !if(P.EmitDstSel, dst_sel{2-0}, ?);
576 let Inst{44-43} = !if(P.EmitDstSel, dst_unused{1-0}, ?);
578 let Inst{47-46} = !if(P.HasSDWAOMod, omod{1-0}, 0);
581 // gfx9 SDWA-B
583 bits<8> sdst; // {vcc_sdst{0}, sdst{6-0}}
585 let Inst{46-40} = !if(P.EmitDst, sdst{6-0}, ?);
707 class VOP_DPPe<VOPProfile P, bit IsDPP16=0> : Enc64 {
715 bit fi;
717 let Inst{39-32} = !if(P.HasSrc0, src0{7-0}, 0);
718 let Inst{48-40} = dpp_ctrl;
725 let Inst{59-56} = bank_mask;
726 let Inst{63-60} = row_mask;
734 bit fi;
741 class VOP3_DPPe_Common_Base<bits<10> op, VOPProfile P> : Enc96 {
751 let Inst{10} = !if(P.HasSrc2Mods, src2_modifiers{1}, 0);
762 let Inst{25-16} = op;
763 let Inst{31-26} = 0x35;
765 let Inst{60-59} = !if(P.HasOMod, omod, 0);
771 class VOP3_DPPe_Common<bits<10> op, VOPProfile P> : VOP3_DPPe_Common_Base<op, P> {
776 let Inst{7-0} = !if(P.EmitDst, vdst{7-0}, 0);
777 let Inst{49-41} = !if(P.HasSrc1, src1, 0);
778 let Inst{58-50} = !if(P.HasSrc2, src2, 0);
789 let Inst{10} = !if(P.HasSrc2Mods, src2_modifiers{1}, 0); // neg_hi src2
795 let Inst{22-16} = op;
796 let Inst{31-23} = 0x198; // encoding
809 let Inst{7-0} = vdst;
810 let Inst{49-41} = !if(P.HasSrc1, src1, 0);
811 let Inst{58-50} = !if(P.HasSrc2, src2, 0);
917 class VOP_DPP <string OpName, VOPProfile P, bit IsDPP16,
922 class VOP3_DPP_Base <string OpName, VOPProfile P, bit IsDPP16,
934 class VOP3_DPP <bits<10> op, string OpName, VOPProfile P, bit IsDPP16,
940 let Inst{40-32} = 0xfa;
941 let Inst{71-64} = !if(P.HasSrc0, src0{7-0}, 0);
942 let Inst{80-72} = dpp_ctrl;
946 // Inst{87-84} ignored by hw
947 let Inst{91-88} = bank_mask;
948 let Inst{95-92} = row_mask;
951 class VOP3P_DPP <bits<7> op, string OpName, VOPProfile P, bit IsDPP16,
959 let Inst{40-32} = 0xfa;
960 let Inst{71-64} = !if(P.HasSrc0, src0{7-0}, 0);
961 let Inst{80-72} = dpp_ctrl;
965 // Inst{87-84} ignored by hw
966 let Inst{91-88} = bank_mask;
967 let Inst{95-92} = row_mask;
975 let Inst{39-32} = !if(P.HasSrc0, src0{7-0}, 0);
976 let Inst{63-40} = dpp8{23-0};
1018 class VOP3_DPP8<bits<10> op, string OpName, VOPProfile P> :
1022 let Inst{40-32} = fi;
1023 let Inst{71-64} = !if(P.HasSrc0, src0{7-0}, 0);
1024 let Inst{95-72} = dpp8{23-0};
1032 let Inst{40-32} = fi;
1033 let Inst{71-64} = !if(P.HasSrc0, src0{7-0}, 0);
1034 let Inst{95-72} = dpp8{23-0};
1064 [{ return N->isDivergent(); }]
1084 [{ return N->isDivergent(); }]> {
1106 // Class for binary integer operations with the clamp bit set for saturation
1114 //===----------------------------------------------------------------------===//
1116 //===----------------------------------------------------------------------===//
1140 class getVOP3PModPat<VOPProfile P, SDPatternOperator node, bit HasExplicitClamp,
1141 bit IsDOT = 0,
1249 class VOP3Features<bit Clamp, bit OpSel, bit Packed, bit MAI> {
1250 bit HasClamp = Clamp;
1251 bit HasOpSel = OpSel;
1252 bit IsPacked = Packed;
1253 bit IsMAI = MAI;
1280 multiclass VOP3Inst_Pseudo_Wrapper<string opName, VOPProfile P, list<dag> pattern = [], bit VOP3Onl…
1284 class VOP3InstBase<string OpName, VOPProfile P, SDPatternOperator node = null_frag, bit IsVOP2 = 0>…
1331 //===----------------------------------------------------------------------===//
1333 //===----------------------------------------------------------------------===//
1335 class Base_VOP3_DPP16<bits<10> op, VOP_DPP_Pseudo ps, string opName = ps.OpName>
1348 class VOP3_DPP16<bits<10> op, VOP_DPP_Pseudo ps, int subtarget,
1352 class VOP3_DPP16_Gen<bits<10> op, VOP_DPP_Pseudo ps, GFXGen Gen,
1361 class Base_VOP3_DPP8<bits<10> op, VOP_Pseudo ps, string opName = ps.OpName>
1374 class Base_VOP3b_DPP16<bits<10> op, VOP_DPP_Pseudo ps,
1378 let Inst{14 - 8} = sdst;
1381 class VOP3b_DPP8_Base<bits<10> op, VOP_Pseudo ps, string opName = ps.OpName>
1384 let Inst{14 - 8} = sdst;
1387 //===----------------------------------------------------------------------===//
1389 //===----------------------------------------------------------------------===//
1391 multiclass VOP3_Real_Base<GFXGen Gen, bits<10> op, string opName = NAME,
1392 bit isSingle = 0> {
1415 multiclass VOP3Dot_Real_Base<GFXGen Gen, bits<10> op, string opName = NAME,
1416 bit isSingle = 0> {
1425 multiclass VOP3_Real_with_name<GFXGen Gen, bits<10> op, string opName,
1426 string asmName, bit isSingle = 0> {
1454 multiclass VOP3_Real_No_Suffix<GFXGen Gen, bits<10> op, string opName = NAME> {
1461 multiclass VOP3_Real_dpp_Base<GFXGen Gen, bits<10> op, string opName = NAME> {
1466 multiclass VOP3Dot_Real_dpp_Base<GFXGen Gen, bits<10> op, string opName = NAME> {
1474 multiclass VOP3_Real_dpp_with_name<GFXGen Gen, bits<10> op, string opName,
1482 multiclass VOP3_Real_dpp8_Base<GFXGen Gen, bits<10> op, string opName = NAME> {
1490 multiclass VOP3Dot_Real_dpp8_Base<GFXGen Gen, bits<10> op, string opName = NAME> {
1500 multiclass VOP3_Real_dpp8_with_name<GFXGen Gen, bits<10> op, string opName,
1512 multiclass VOP3be_Real<GFXGen Gen, bits<10> op, string opName, string asmName,
1513 bit isSingle = 0> {
1521 multiclass VOP3be_Real_dpp<GFXGen Gen, bits<10> op, string opName,
1532 multiclass VOP3be_Real_dpp8<GFXGen Gen, bits<10> op, string opName,
1542 multiclass VOP3_Realtriple<GFXGen Gen, bits<10> op, bit isSingle = 0,
1548 multiclass VOP3Dot_Realtriple<GFXGen Gen, bits<10> op, bit isSingle = 0,
1554 multiclass VOP3Only_Realtriple<GFXGen Gen, bits<10> op> :
1557 multiclass VOP3_Realtriple_with_name<GFXGen Gen, bits<10> op, string opName,
1558 string asmName, bit isSingle = 0> :
1563 multiclass VOP3Only_Realtriple_with_name<GFXGen Gen, bits<10> op, string opName,
1567 multiclass VOP3Only_Realtriple_t16<GFXGen Gen, bits<10> op, string asmName,
1572 GFXGen Gen, bits<10> op, bit isSingle = 0, string opName = NAME,
1578 multiclass VOP3beOnly_Realtriple<GFXGen Gen, bits<10> op> :
1581 //===----------------------------------------------------------------------===//
1583 //===----------------------------------------------------------------------===//
1585 multiclass VOP3be_Real_gfx11<bits<10> op, string opName, string asmName,
1586 bit isSingle = 0> :
1589 multiclass VOP3_Real_Base_gfx11<bits<10> op, string opName = NAME,
1590 bit isSingle = 0> :
1593 multiclass VOP3_Realtriple_gfx11<bits<10> op, bit isSingle = 0,
1597 multiclass VOP3Only_Realtriple_t16_gfx11<bits<10> op, string asmName,
1601 //===----------------------------------------------------------------------===//
1603 //===----------------------------------------------------------------------===//
1605 multiclass VOP3Only_Realtriple_gfx12<bits<10> op, bit isSingle = 0> :
1610 multiclass VOP3Only_Real_Base_gfx12<bits<10> op> :
1613 multiclass VOP3Only_Realtriple_t16_gfx12<bits<10> op> :
1616 multiclass VOP3be_Real_with_name_gfx12<bits<10> op, string opName,
1617 string asmName, bit isSingle = 0> {
1629 multiclass VOP3_Realtriple_with_name_gfx12<bits<10> op, string opName,
1630 string asmName, bit isSingle = 0> :
1633 multiclass VOP3Only_Realtriple_with_name_gfx11_gfx12<bits<10> op, string opName,
1638 multiclass VOP3Only_Realtriple_with_name_t16_gfx12<bits<10> op, string asmName,
1642 //===----------------------------------------------------------------------===//