Lines Matching full:src0
33 (ins FP16InputMods:$src0_modifiers, VCSrc_f16:$src0,
37 (ins FPVRegInputMods:$src0_modifiers, VGPRSrc_32:$src0,
130 (pat (v2i16 (VOP3PMods v2i16:$src0, i32:$src0_modifiers)),
132 (inst $src0_modifiers, $src0, $src1_modifiers, $src1, DSTCLAMP.ENABLE)
151 (f32 (fma_like (f32 (VOP3PMadMixModsExt f16:$src0, i32:$src0_mods)),
154 (mix_inst $src0_mods, $src0, $src1_mods, $src1, $src2_mods, $src2,
157 (f32 (fma_like (f32 (VOP3PMadMixMods f16:$src0, i32:$src0_mods)),
160 (mix_inst $src0_mods, $src0, $src1_mods, $src1, $src2_mods, $src2,
163 (f32 (fma_like (f32 (VOP3PMadMixMods f16:$src0, i32:$src0_mods)),
166 (mix_inst $src0_mods, $src0, $src1_mods, $src1, $src2_mods, $src2,
170 (f16 (fpround (fma_like (f32 (VOP3PMadMixMods f16:$src0, i32:$src0_modifiers)),
173 (mixlo_inst $src0_modifiers, $src0,
184 …(build_vector f16:$elt0, (f16 (fpround (fma_like (f32 (VOP3PMadMixMods f16:$src0, i32:$src0_modifi…
187 (v2f16 (mixhi_inst $src0_modifiers, $src0,
197 (AMDGPUclamp (f16 (fpround (fma_like (f32 (VOP3PMadMixMods f16:$src0, i32:$src0_modifiers)),
200 (v2f16 (mixhi_inst $src0_modifiers, $src0,
227 (f16 (fpround (fmul (f32 (VOP3PMadMixMods f32:$src0, i32:$src0_modifiers)),
229 (mixlo_inst $src0_modifiers, $src0,
237 …(build_vector f16:$elt0, (f16 (fpround (fmul (f32 (VOP3PMadMixMods f32:$src0, i32:$src0_modifiers)…
239 (v2f16 (mixhi_inst $src0_modifiers, $src0,
319 (ops node:$src0, node:$src1),
321 (!cast<Extract>(Type#Index#"_8bit") node:$src0),
346 (ops node:$src0, node:$src1),
348 (!cast<Extract>(Type#Index#"_4bit") node:$src0),
353 (add (add_oneuse (AMDGPUmul_u24_oneuse (srl i32:$src0, (i32 16)),
355 (AMDGPUmul_u24_oneuse (and i32:$src0, (i32 65535)),
358 (Inst (i32 8), $src0, (i32 8), $src1, (i32 8), $src2, (i1 0))> {
363 (add (add_oneuse (AMDGPUmul_i24_oneuse (sra i32:$src0, (i32 16)),
365 (AMDGPUmul_i24_oneuse (sext_inreg i32:$src0, i16),
367 (Inst (i32 8), $src0, (i32 8), $src1, (i32 8), $src2, (i1 0))> {
422 def : GCNPat < (intrinsic_node (VOP3PModsNeg i32:$src0_mods), i32:$src0,
425 (!cast<Instruction>(NAME) $src0_mods, i32:$src0,
435 def : GCNPat < (int_amdgcn_sdot8 i32:$src0,
438 (V_DOT8_I32_IU4 (i32 9), i32:$src0,
442 def : GCNPat < (int_amdgcn_sdot4 i32:$src0,
445 (V_DOT4_I32_IU8 (i32 9), i32:$src0,
450 // Does not use opsel, no src_modifiers on src0 and src1.
462 let InsVOP3P = (ins VSrc_b32:$src0, VSrc_b32:$src1,
466 let InsVOP3DPP8 = (ins DstRC:$old, VGPR_32:$src0, VRegSrc_32:$src1,
470 let InsVOP3DPP16 = (ins DstRC:$old, VGPR_32:$src0, VRegSrc_32:$src1,
481 def : GCNPat <(intrinsic_node i32:$src0, i32:$src1,
483 (!cast<Instruction>(NAME) i32:$src0, i32:$src1,
501 … (add_oneuse lhs, (!cast<PatFrag>("Mul"#Type#"_Elt"#y) i32:$src0, i32:$src1)))),
502 …(!cast<VOP3P_Pseudo>("V_DOT4_"#Type#"32_"#Type#8) (i32 8), $src0, (i32 8), $src1, (i32 8), $src2, …
507 …!cast<dag>(!foldl((add_oneuse i32:$src2, (!cast<PatFrag>("Mul"#Type#"0_4bit") i32:$src0, i32:$src1…
509 … (NonACAdd_oneuse lhs, (!cast<PatFrag>("Mul"#Type#y#"_4bit") i32:$src0, i32:$src1)))),
510 …(!cast<VOP3P_Pseudo>("V_DOT8_"#Type#"32_"#Type#4) (i32 8), $src0, (i32 8), $src1, (i32 8), $src2, …
517 …!cast<dag>(!foldl((add_oneuse i32:$src2, (!cast<PatFrag>("Mul"#Type#"0_4bit") i32:$src0, i32:$src1…
519 … (NonACAdd_oneuse lhs, (!cast<PatFrag>("Mul"#Type#y#"_4bit") i32:$src0, i32:$src1)))),
520 …(!cast<VOP3P_Pseudo>("V_DOT8_"#Type#"32_"#Type#4) (i32 8), $src0, (i32 8), $src1, (i32 8), $src2, …
555 let AsmVOP3Base = "$vdst, $src0, $src1, $src2$cbsz$abid$blgp";
556 …let Ins64 = (ins Src0RC64:$src0, Src1RC64:$src1, Src2RC64:$src2, CBSZ:$cbsz, ABID:$abid, blgp:$blg…
561 // actual HW restriction. In particular earlyclobber also affects src0 and
571 let Asm64 = " $vdst, $src0, $src1, $idx$cbsz$abid";
573 …let Ins64 = (ins Src0RC64:$src0, Src1RC64:$src1, VRegSrc_32:$idx, CBSZ:$cbsz, ABID:$abid, Src2RC64…
639 (ops node:$src0, node:$src1, node:$src2, node:$cbsz, node:$abid, node:$blgp),
640 (Op $src0, $src1, $src2, $cbsz, $abid, $blgp),
862 (P.Src0VT (VOP3PMods P.Src0VT:$src0, i32:$src0_modifiers)),
866 …(P.DstVT (Inst i32:$src0_modifiers, P.Src0VT:$src0, i32:$src1_modifiers, P.Src1VT:$src1, $src2_mod…
871 (P.Src0VT P.Src0VT:$src0),
875 …(P.DstVT (Inst (i32 8), P.Src0VT:$src0, (i32 8), P.Src1VT:$src1, i32:$src2_modifiers, P.Src2VT:$sr…
880 (VOP3PModsNeg i32:$src0_modifiers), (P.Src0VT P.Src0VT:$src0),
884 …(P.DstVT (Inst i32:$src0_modifiers, P.Src0VT:$src0, i32:$src1_modifiers, P.Src1VT:$src1, (i32 8), …
1024 // Opcode | src0/src1 - matrix A/B | src2 - matrix C or Index
1068 let InsVOP3P = !con(Src0Mods, (ins Src0RC64:$src0), Src1Mods, (ins Src1RC64:$src1),
1083 let AsmVOP3P = "$vdst, $src0, $src1, $src2"#IndexKeyAsm#NegAsm#ClampAsm;
1087 …dag Src0InPat = !cond(IsAB_F16 : (ins (Src0VT (WMMAModsF16Neg Src0VT:$src0, i32:$src0_modifiers)…
1088 IsAB_BF16 : (ins Src0VT:$src0),
1089 IsIU : (ins (VOP3PModsNeg i32:$src0_modifiers), Src0VT:$src0),
1090 IsFP8BF8 : (ins Src0VT:$src0));
1091 dag Src0OutPat = !cond(IsAB_F16 : (ins i32:$src0_modifiers, Src0VT:$src0),
1092 IsAB_BF16 : (ins (i32 8), Src0VT:$src0),
1093 IsIU : (ins i32:$src0_modifiers, Src0VT:$src0),
1094 IsFP8BF8 : (ins Src0VT:$src0));
1618 Pfl_ACD.Src0RC64:$src0, Pfl_ACD.Src1RC64:$src1, Pfl_ACD.Src2RC64:$src2,
1622 Pfl_VCD.Src0RC64:$src0, Pfl_VCD.Src1RC64:$src1, Pfl_VCD.Src2RC64:$src2,