Lines Matching +full:0 +full:x33c
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
14 let HasExtVOP3DPP = 0;
15 let HasExtDPP = 0;
28 let HasExtVOP3DPP = 0;
29 let HasExtDPP = 0;
44 let HasExtVOP3DPP = 0;
45 let HasExtDPP = 0;
49 let HasExtVOP3DPP = 0;
50 let HasExtDPP = 0;
60 let mayRaiseFPException = 0;
80 let HasSrc0Mods = 0;
129 let mayRaiseFPException = 0 in {
167 let SubtargetPredicate = isGFX12Plus, ReadsModeReg = 0 in {
177 } // End SubtargetPredicate = isGFX12Plus, ReadsModeReg = 0
201 let mayRaiseFPException = 0 in {
215 let mayRaiseFPException = 0 in {
227 } // End mayRaiseFPException = 0
229 let SubtargetPredicate = isGFX12Plus, ReadsModeReg = 0 in {
232 } // End SubtargetPredicate = isGFX12Plus, ReadsModeReg = 0
251 let mayRaiseFPException = 0 in { // Seems suspicious but manual doesn't say it does.
258 } // End mayRaiseFPException = 0
295 (i32 (V_BFE_I32_e64 i16:$src, (i32 0), (i32 0x10)))
311 let HasModifiers = 0;
401 (i32 (V_BFE_I32_e64 $src, (S_MOV_B32 (i32 0)), (S_MOV_B32 (i32 0x10)))), sub0,
403 …(V_ASHRREV_I32_e32 (S_MOV_B32 (i32 0x1f)), (i32 (V_BFE_I32_e64 $src, (S_MOV_B32 (i32 0)), (S_MOV_B…
413 // Note: 16-bit instructions produce a 0 result in the high 16-bits
433 (inst i16:$src0, i16:$src1, i16:$src2, (i1 0))
467 unsigned ConstantBusUses = 0;
468 for (unsigned i = 0; i < 3; ++i) {
494 int ConstantBusUses = 0;
495 for (unsigned i = 0; i < 3; ++i) {
515 int64_t Imm = 0;
545 let HasClamp = 0;
566 let HasClamp = 0;
567 let HasSrc2 = 0;
577 HasOMod, 0, 1, HasSrc0FloatMods,
582 HasOMod, 0, 1, HasSrc0FloatMods,
590 let HasClamp = 0;
636 let SubtargetPredicate = isGFX12Plus, ReadsModeReg = 0 in {
639 } // End SubtargetPredicate = isGFX12Plus, ReadsModeReg = 0
658 // V_LSHL_ADD_U64: D0.u64 = (S0.u64 << S1.u[2:0]) + S2.u64
659 // src0 is shifted left by 0-4 (use “0” to get ADD_U64).
663 let OtherPredicates = [HasFP8ConversionInsts], mayRaiseFPException = 0,
686 (inst !if(index, SRCMODS.DST_OP_SEL, 0), $src0, 0, $src1, $old, 0)
691 (inst !if(index{1}, SRCMODS.DST_OP_SEL, 0), $src0, 0, $src1,
692 !if(index{0}, SRCMODS.OP_SEL_0, 0), $old, 0)
702 foreach Index = [0, -1] in {
708 foreach Index = [0, 1, 2, 3] in {
762 (inst $src0_modifiers, $src0, $src1_modifiers, $src1, DSTCLAMP.ENABLE, 0)
776 0 /* clamp */),
788 0 /* clamp */),
796 (EXTRACT_SUBREG (inst i32:$src0, i32:$src1, (i64 (as_i64imm $src2)), 0 /* clamp */), sub0)
804 (inst $src0, $src1, $src2, 0 /* clamp */)
822 let HasClamp = 0;
823 let HasExtVOP3DPP = 0;
824 let HasExtDPP = 0;
831 let HasClamp = 0;
832 let HasExtVOP3DPP = 0;
833 let HasExtDPP = 0;
849 SCSrc_b32:$src1, 0, SCSrc_b32:$src2, VGPR_32:$vdst_in)
886 (V_SUB_NC_U16_e64 0, VSrc_b16:$src0, 0, NegSubInlineIntConst16:$src1, 0, 0)
921 let HasClamp = 0;
922 let HasOMod = 0;
938 let SubtargetPredicate = isGFX12Plus, ReadsModeReg = 0 in {
943 } // End SubtargetPredicate = isGFX12Plus, ReadsModeReg = 0
1007 dag ret3 = (inst P.Src0VT:$src0, P.Src1VT:$src1, P.Src2VT:$src2, (i1 0));
1008 dag ret2 = (inst P.Src0VT:$src0, P.Src1VT:$src1, (i1 0));
1009 dag ret1 = (inst P.Src0VT:$src0, (i1 0));
1041 defm V_MIN3_NUM_F32 : VOP3_Realtriple_with_name_gfx12<0x229, "V_MIN3_F32", "v_min3_num_f32">;
1042 defm V_MAX3_NUM_F32 : VOP3_Realtriple_with_name_gfx12<0x22a, "V_MAX3_F32", "v_max3_num_f32">;
1043 defm V_MIN3_NUM_F16 : VOP3_Realtriple_with_name_gfx12<0x22b, "V_MIN3_F16", "v_min3_num_f16">;
1044 defm V_MAX3_NUM_F16 : VOP3_Realtriple_with_name_gfx12<0x22c, "V_MAX3_F16", "v_max3_num_f16">;
1045 defm V_MINIMUM3_F32 : VOP3Only_Realtriple_gfx12<0x22d>;
1046 defm V_MAXIMUM3_F32 : VOP3Only_Realtriple_gfx12<0x22e>;
1047 defm V_MINIMUM3_F16 : VOP3Only_Realtriple_t16_gfx12<0x22f>;
1048 defm V_MAXIMUM3_F16 : VOP3Only_Realtriple_t16_gfx12<0x230>;
1049 defm V_MED3_NUM_F32 : VOP3_Realtriple_with_name_gfx12<0x231, "V_MED3_F32", "v_med3_num_f32">;
1050 defm V_MED3_NUM_F16 : VOP3_Realtriple_with_name_gfx12<0x232, "V_MED3_F16", "v_med3_num_f16">;
1051 defm V_MINMAX_NUM_F32 : VOP3_Realtriple_with_name_gfx12<0x268, "V_MINMAX_F32", "v_minmax_num_f3…
1052 defm V_MAXMIN_NUM_F32 : VOP3_Realtriple_with_name_gfx12<0x269, "V_MAXMIN_F32", "v_maxmin_num_f3…
1053 defm V_MINMAX_NUM_F16 : VOP3_Realtriple_with_name_gfx12<0x26a, "V_MINMAX_F16", "v_minmax_num_f1…
1054 defm V_MAXMIN_NUM_F16 : VOP3_Realtriple_with_name_gfx12<0x26b, "V_MAXMIN_F16", "v_maxmin_num_f1…
1055 defm V_MINIMUMMAXIMUM_F32 : VOP3Only_Realtriple_gfx12<0x26c>;
1056 defm V_MAXIMUMMINIMUM_F32 : VOP3Only_Realtriple_gfx12<0x26d>;
1057 defm V_MINIMUMMAXIMUM_F16 : VOP3Only_Realtriple_t16_gfx12<0x26e>;
1058 defm V_MAXIMUMMINIMUM_F16 : VOP3Only_Realtriple_t16_gfx12<0x26f>;
1059 defm V_S_EXP_F32 : VOP3Only_Real_Base_gfx12<0x280>;
1060 defm V_S_EXP_F16 : VOP3Only_Real_Base_gfx12<0x281>;
1061 defm V_S_LOG_F32 : VOP3Only_Real_Base_gfx12<0x282>;
1062 defm V_S_LOG_F16 : VOP3Only_Real_Base_gfx12<0x283>;
1063 defm V_S_RCP_F32 : VOP3Only_Real_Base_gfx12<0x284>;
1064 defm V_S_RCP_F16 : VOP3Only_Real_Base_gfx12<0x285>;
1065 defm V_S_RSQ_F32 : VOP3Only_Real_Base_gfx12<0x286>;
1066 defm V_S_RSQ_F16 : VOP3Only_Real_Base_gfx12<0x287>;
1067 defm V_S_SQRT_F32 : VOP3Only_Real_Base_gfx12<0x288>;
1068 defm V_S_SQRT_F16 : VOP3Only_Real_Base_gfx12<0x289>;
1069 defm V_MAD_CO_U64_U32 : VOP3be_Real_with_name_gfx12<0x2fe, "V_MAD_U64_U32", "v_mad_co_u64_u32">;
1070 defm V_MAD_CO_I64_I32 : VOP3be_Real_with_name_gfx12<0x2ff, "V_MAD_I64_I32", "v_mad_co_i64_i32">;
1071 defm V_MINIMUM_F64 : VOP3Only_Real_Base_gfx12<0x341>;
1072 defm V_MAXIMUM_F64 : VOP3Only_Real_Base_gfx12<0x342>;
1073 defm V_MINIMUM_F32 : VOP3Only_Realtriple_gfx12<0x365>;
1074 defm V_MAXIMUM_F32 : VOP3Only_Realtriple_gfx12<0x366>;
1075 defm V_MINIMUM_F16 : VOP3Only_Realtriple_t16_gfx12<0x367>;
1076 defm V_MAXIMUM_F16 : VOP3Only_Realtriple_t16_gfx12<0x368>;
1078 defm V_PERMLANE16_VAR_B32 : VOP3Only_Real_Base_gfx12<0x30f>;
1079 defm V_PERMLANEX16_VAR_B32 : VOP3Only_Real_Base_gfx12<0x310>;
1081 defm V_CVT_PK_FP8_F32 : VOP3Only_Realtriple_gfx12<0x369>;
1082 defm V_CVT_PK_BF8_F32 : VOP3Only_Realtriple_gfx12<0x36a>;
1083 defm V_CVT_SR_FP8_F32_gfx12 : VOP3_Realtriple_with_name_gfx12<0x36b, "V_CVT_SR_FP8_F32_gfx12", "v_c…
1084 defm V_CVT_SR_BF8_F32_gfx12 : VOP3_Realtriple_with_name_gfx12<0x36c, "V_CVT_SR_BF8_F32_gfx12", "v_c…
1116 defm V_FMA_DX9_ZERO_F32 : VOP3_Real_with_name_gfx11_gfx12<0x209, "V_FMA_LEGACY_F32", "v_fma_dx9_…
1117 defm V_MAD_I32_I24 : VOP3_Realtriple_gfx11_gfx12<0x20a>;
1118 defm V_MAD_U32_U24 : VOP3_Realtriple_gfx11_gfx12<0x20b>;
1119 defm V_CUBEID_F32 : VOP3_Realtriple_gfx11_gfx12<0x20c>;
1120 defm V_CUBESC_F32 : VOP3_Realtriple_gfx11_gfx12<0x20d>;
1121 defm V_CUBETC_F32 : VOP3_Realtriple_gfx11_gfx12<0x20e>;
1122 defm V_CUBEMA_F32 : VOP3_Realtriple_gfx11_gfx12<0x20f>;
1123 defm V_BFE_U32 : VOP3_Realtriple_gfx11_gfx12<0x210>;
1124 defm V_BFE_I32 : VOP3_Realtriple_gfx11_gfx12<0x211>;
1125 defm V_BFI_B32 : VOP3_Realtriple_gfx11_gfx12<0x212>;
1126 defm V_FMA_F32 : VOP3_Realtriple_gfx11_gfx12<0x213>;
1127 defm V_FMA_F64 : VOP3_Real_Base_gfx11_gfx12<0x214>;
1128 defm V_LERP_U8 : VOP3_Realtriple_gfx11_gfx12<0x215>;
1129 defm V_ALIGNBIT_B32 : VOP3_Realtriple_gfx11_gfx12<0x216>;
1130 defm V_ALIGNBYTE_B32 : VOP3_Realtriple_gfx11_gfx12<0x217>;
1131 defm V_MULLIT_F32 : VOP3_Realtriple_gfx11_gfx12<0x218>;
1132 defm V_MIN3_F32 : VOP3_Realtriple_gfx11<0x219>;
1133 defm V_MIN3_I32 : VOP3_Realtriple_gfx11_gfx12<0x21a>;
1134 defm V_MIN3_U32 : VOP3_Realtriple_gfx11_gfx12<0x21b>;
1135 defm V_MAX3_F32 : VOP3_Realtriple_gfx11<0x21c>;
1136 defm V_MAX3_I32 : VOP3_Realtriple_gfx11_gfx12<0x21d>;
1137 defm V_MAX3_U32 : VOP3_Realtriple_gfx11_gfx12<0x21e>;
1138 defm V_MED3_F32 : VOP3_Realtriple_gfx11<0x21f>;
1139 defm V_MED3_I32 : VOP3_Realtriple_gfx11_gfx12<0x220>;
1140 defm V_MED3_U32 : VOP3_Realtriple_gfx11_gfx12<0x221>;
1141 defm V_SAD_U8 : VOP3_Realtriple_gfx11_gfx12<0x222>;
1142 defm V_SAD_HI_U8 : VOP3_Realtriple_gfx11_gfx12<0x223>;
1143 defm V_SAD_U16 : VOP3_Realtriple_gfx11_gfx12<0x224>;
1144 defm V_SAD_U32 : VOP3_Realtriple_gfx11_gfx12<0x225>;
1145 defm V_CVT_PK_U8_F32 : VOP3_Realtriple_gfx11_gfx12<0x226>;
1146 defm V_DIV_FIXUP_F32 : VOP3_Real_Base_gfx11_gfx12<0x227>;
1147 defm V_DIV_FIXUP_F64 : VOP3_Real_Base_gfx11_gfx12<0x228>;
1148 defm V_DIV_FMAS_F32 : VOP3_Real_Base_gfx11_gfx12<0x237>;
1149 defm V_DIV_FMAS_F64 : VOP3_Real_Base_gfx11_gfx12<0x238>;
1150 defm V_MSAD_U8 : VOP3_Realtriple_gfx11_gfx12<0x239>;
1151 defm V_QSAD_PK_U16_U8 : VOP3_Real_Base_gfx11_gfx12<0x23a>;
1152 defm V_MQSAD_PK_U16_U8 : VOP3_Real_Base_gfx11_gfx12<0x23b>;
1153 defm V_MQSAD_U32_U8 : VOP3_Real_Base_gfx11_gfx12<0x23d>;
1154 defm V_XOR3_B32 : VOP3_Realtriple_gfx11_gfx12<0x240>;
1155 defm V_MAD_U16 : VOP3_Realtriple_with_name_gfx11_gfx12<0x241, "V_MAD_U16_gfx9", "v_mad_…
1156 defm V_PERM_B32 : VOP3_Realtriple_gfx11_gfx12<0x244>;
1157 defm V_XAD_U32 : VOP3_Realtriple_gfx11_gfx12<0x245>;
1158 defm V_LSHL_ADD_U32 : VOP3_Realtriple_gfx11_gfx12<0x246>;
1159 defm V_ADD_LSHL_U32 : VOP3_Realtriple_gfx11_gfx12<0x247>;
1160 defm V_FMA_F16 : VOP3_Realtriple_with_name_gfx11_gfx12<0x248, "V_FMA_F16_gfx9", "v_fma_…
1161 defm V_MIN3_F16 : VOP3_Realtriple_gfx11<0x249>;
1162 defm V_MIN3_I16 : VOP3_Realtriple_gfx11_gfx12<0x24a>;
1163 defm V_MIN3_U16 : VOP3_Realtriple_gfx11_gfx12<0x24b>;
1164 defm V_MAX3_F16 : VOP3_Realtriple_gfx11<0x24c>;
1165 defm V_MAX3_I16 : VOP3_Realtriple_gfx11_gfx12<0x24d>;
1166 defm V_MAX3_U16 : VOP3_Realtriple_gfx11_gfx12<0x24e>;
1167 defm V_MED3_F16 : VOP3_Realtriple_gfx11<0x24f>;
1168 defm V_MED3_I16 : VOP3_Realtriple_gfx11_gfx12<0x250>;
1169 defm V_MED3_U16 : VOP3_Realtriple_gfx11_gfx12<0x251>;
1170 defm V_MAD_I16 : VOP3_Realtriple_with_name_gfx11_gfx12<0x253, "V_MAD_I16_gfx9", "v_mad_…
1171 defm V_DIV_FIXUP_F16 : VOP3_Realtriple_with_name_gfx11_gfx12<0x254, "V_DIV_FIXUP_F16_gfx9", "…
1172 defm V_ADD3_U32 : VOP3_Realtriple_gfx11_gfx12<0x255>;
1173 defm V_LSHL_OR_B32 : VOP3_Realtriple_gfx11_gfx12<0x256>;
1174 defm V_AND_OR_B32 : VOP3_Realtriple_gfx11_gfx12<0x257>;
1175 defm V_OR3_B32 : VOP3_Realtriple_gfx11_gfx12<0x258>;
1176 defm V_MAD_U32_U16 : VOP3_Realtriple_gfx11_gfx12<0x259>;
1177 defm V_MAD_I32_I16 : VOP3_Realtriple_gfx11_gfx12<0x25a>;
1178 defm V_PERMLANE16_B32 : VOP3_Real_Base_gfx11_gfx12<0x25b>;
1179 defm V_PERMLANEX16_B32 : VOP3_Real_Base_gfx11_gfx12<0x25c>;
1180 defm V_MAXMIN_F32 : VOP3_Realtriple_gfx11<0x25e>;
1181 defm V_MINMAX_F32 : VOP3_Realtriple_gfx11<0x25f>;
1182 defm V_MAXMIN_F16 : VOP3_Realtriple_gfx11<0x260>;
1183 defm V_MINMAX_F16 : VOP3_Realtriple_gfx11<0x261>;
1184 defm V_MAXMIN_U32 : VOP3_Realtriple_gfx11_gfx12<0x262>;
1185 defm V_MINMAX_U32 : VOP3_Realtriple_gfx11_gfx12<0x263>;
1186 defm V_MAXMIN_I32 : VOP3_Realtriple_gfx11_gfx12<0x264>;
1187 defm V_MINMAX_I32 : VOP3_Realtriple_gfx11_gfx12<0x265>;
1188 defm V_DOT2_F16_F16 : VOP3Dot_Realtriple_gfx11_gfx12<0x266>;
1189 defm V_DOT2_BF16_BF16 : VOP3Dot_Realtriple_gfx11_gfx12<0x267>;
1190 defm V_DIV_SCALE_F32 : VOP3be_Real_gfx11_gfx12<0x2fc, "V_DIV_SCALE_F32", "v_div_scale_f32">;
1191 defm V_DIV_SCALE_F64 : VOP3be_Real_gfx11_gfx12<0x2fd, "V_DIV_SCALE_F64", "v_div_scale_f64">;
1192 defm V_MAD_U64_U32_gfx11 : VOP3be_Real_gfx11<0x2fe, "V_MAD_U64_U32_gfx11", "v_mad_u64_u32">;
1193 defm V_MAD_I64_I32_gfx11 : VOP3be_Real_gfx11<0x2ff, "V_MAD_I64_I32_gfx11", "v_mad_i64_i32">;
1194 defm V_ADD_NC_U16 : VOP3Only_Realtriple_gfx11_gfx12<0x303>;
1195 defm V_SUB_NC_U16 : VOP3Only_Realtriple_gfx11_gfx12<0x304>;
1196 defm V_MUL_LO_U16_t16 : VOP3Only_Realtriple_t16_gfx11_gfx12<0x305, "v_mul_lo_u16">;
1197 defm V_CVT_PK_I16_F32 : VOP3_Realtriple_gfx11_gfx12<0x306>;
1198 defm V_CVT_PK_U16_F32 : VOP3_Realtriple_gfx11_gfx12<0x307>;
1199 defm V_MAX_U16_t16 : VOP3Only_Realtriple_t16_gfx11_gfx12<0x309, "v_max_u16">;
1200 defm V_MAX_I16_t16 : VOP3Only_Realtriple_t16_gfx11_gfx12<0x30a, "v_max_i16">;
1201 defm V_MIN_U16_t16 : VOP3Only_Realtriple_t16_gfx11_gfx12<0x30b, "v_min_u16">;
1202 defm V_MIN_I16_t16 : VOP3Only_Realtriple_t16_gfx11_gfx12<0x30c, "v_min_i16">;
1203 defm V_ADD_NC_I16 : VOP3_Realtriple_with_name_gfx11_gfx12<0x30d, "V_ADD_I16", "v_add_nc_i1…
1204 defm V_SUB_NC_I16 : VOP3_Realtriple_with_name_gfx11_gfx12<0x30e, "V_SUB_I16", "v_sub_nc_i1…
1205 defm V_PACK_B32_F16 : VOP3_Realtriple_gfx11_gfx12<0x311>;
1206 defm V_CVT_PK_NORM_I16_F16 : VOP3_Realtriple_with_name_gfx11_gfx12<0x312, "V_CVT_PKNORM_I16_F16" , …
1207 defm V_CVT_PK_NORM_U16_F16 : VOP3_Realtriple_with_name_gfx11_gfx12<0x313, "V_CVT_PKNORM_U16_F16" , …
1208 defm V_SUB_NC_I32 : VOP3_Realtriple_with_name_gfx11_gfx12<0x325, "V_SUB_I32", "v_sub_nc_i3…
1209 defm V_ADD_NC_I32 : VOP3_Realtriple_with_name_gfx11_gfx12<0x326, "V_ADD_I32", "v_add_nc_i3…
1210 defm V_ADD_F64 : VOP3_Real_Base_gfx11<0x327>;
1211 defm V_MUL_F64 : VOP3_Real_Base_gfx11<0x328>;
1212 defm V_MIN_F64 : VOP3_Real_Base_gfx11<0x329>;
1213 defm V_MAX_F64 : VOP3_Real_Base_gfx11<0x32a>;
1214 defm V_LDEXP_F64 : VOP3_Real_Base_gfx11_gfx12<0x32b>;
1215 defm V_MUL_LO_U32 : VOP3_Real_Base_gfx11_gfx12<0x32c>;
1216 defm V_MUL_HI_U32 : VOP3_Real_Base_gfx11_gfx12<0x32d>;
1217 defm V_MUL_HI_I32 : VOP3_Real_Base_gfx11_gfx12<0x32e>;
1218 defm V_TRIG_PREOP_F64 : VOP3_Real_Base_gfx11_gfx12<0x32f>;
1219 defm V_LSHLREV_B16_t16 : VOP3Only_Realtriple_t16_gfx11_gfx12<0x338, "v_lshlrev_b16">;
1220 defm V_LSHRREV_B16_t16 : VOP3Only_Realtriple_t16_gfx11_gfx12<0x339, "v_lshrrev_b16">;
1221 defm V_ASHRREV_I16_t16 : VOP3Only_Realtriple_t16_gfx11_gfx12<0x33a, "v_ashrrev_i16">;
1222 defm V_LSHLREV_B64 : VOP3_Real_Base_gfx11<0x33c>;
1223 defm V_LSHRREV_B64 : VOP3_Real_Base_gfx11_gfx12<0x33d>;
1224 defm V_ASHRREV_I64 : VOP3_Real_Base_gfx11_gfx12<0x33e>;
1225 defm V_READLANE_B32 : VOP3_Real_No_Suffix_gfx11_gfx12<0x360>; // Pseudo in VOP2
1227 defm V_WRITELANE_B32 : VOP3_Real_No_Suffix_gfx11_gfx12<0x361>; // Pseudo in VOP2
1229 defm V_AND_B16_t16 : VOP3Only_Realtriple_t16_gfx11_gfx12<0x362, "v_and_b16">;
1230 defm V_OR_B16_t16 : VOP3Only_Realtriple_t16_gfx11_gfx12<0x363, "v_or_b16">;
1231 defm V_XOR_B16_t16 : VOP3Only_Realtriple_t16_gfx11_gfx12<0x364, "v_xor_b16">;
1285 defm V_READLANE_B32 : VOP3_Real_No_Suffix_gfx10<0x360>;
1287 defm V_WRITELANE_B32 : VOP3_Real_No_Suffix_gfx10<0x361>;
1292 defm V_MUL_LO_I32 : VOP3_Real_gfx10<0x16b>;
1295 defm V_XOR3_B32 : VOP3_Real_gfx10<0x178>;
1296 defm V_LSHLREV_B64 : VOP3_Real_gfx10<0x2ff>;
1297 defm V_LSHRREV_B64 : VOP3_Real_gfx10<0x300>;
1298 defm V_ASHRREV_I64 : VOP3_Real_gfx10<0x301>;
1299 defm V_PERM_B32 : VOP3_Real_gfx10<0x344>;
1300 defm V_XAD_U32 : VOP3_Real_gfx10<0x345>;
1301 defm V_LSHL_ADD_U32 : VOP3_Real_gfx10<0x346>;
1302 defm V_ADD_LSHL_U32 : VOP3_Real_gfx10<0x347>;
1303 defm V_ADD3_U32 : VOP3_Real_gfx10<0x36d>;
1304 defm V_LSHL_OR_B32 : VOP3_Real_gfx10<0x36f>;
1305 defm V_AND_OR_B32 : VOP3_Real_gfx10<0x371>;
1306 defm V_OR3_B32 : VOP3_Real_gfx10<0x372>;
1310 VOP3OpSel_Real_gfx10_with_name<0x30d, "V_ADD_I16", "v_add_nc_i16">;
1312 VOP3OpSel_Real_gfx10_with_name<0x30e, "V_SUB_I16", "v_sub_nc_i16">;
1314 VOP3_Real_gfx10_with_name<0x376, "V_SUB_I32", "v_sub_nc_i32">;
1316 VOP3_Real_gfx10_with_name<0x37f, "V_ADD_I32", "v_add_nc_i32">;
1318 defm V_INTERP_P1_F32_e64 : VOP3Interp_Real_gfx10<0x200>;
1319 defm V_INTERP_P2_F32_e64 : VOP3Interp_Real_gfx10<0x201>;
1320 defm V_INTERP_MOV_F32_e64 : VOP3Interp_Real_gfx10<0x202>;
1322 defm V_INTERP_P1LL_F16 : VOP3Interp_Real_gfx10<0x342>;
1323 defm V_INTERP_P1LV_F16 : VOP3Interp_Real_gfx10<0x343>;
1324 defm V_INTERP_P2_F16 : VOP3Interp_Real_gfx10<0x35a>;
1326 defm V_PACK_B32_F16 : VOP3OpSel_Real_gfx10<0x311>;
1327 defm V_CVT_PKNORM_I16_F16 : VOP3OpSel_Real_gfx10<0x312>;
1328 defm V_CVT_PKNORM_U16_F16 : VOP3OpSel_Real_gfx10<0x313>;
1330 defm V_MIN3_F16 : VOP3OpSel_Real_gfx10<0x351>;
1331 defm V_MIN3_I16 : VOP3OpSel_Real_gfx10<0x352>;
1332 defm V_MIN3_U16 : VOP3OpSel_Real_gfx10<0x353>;
1333 defm V_MAX3_F16 : VOP3OpSel_Real_gfx10<0x354>;
1334 defm V_MAX3_I16 : VOP3OpSel_Real_gfx10<0x355>;
1335 defm V_MAX3_U16 : VOP3OpSel_Real_gfx10<0x356>;
1336 defm V_MED3_F16 : VOP3OpSel_Real_gfx10<0x357>;
1337 defm V_MED3_I16 : VOP3OpSel_Real_gfx10<0x358>;
1338 defm V_MED3_U16 : VOP3OpSel_Real_gfx10<0x359>;
1339 defm V_MAD_U32_U16 : VOP3OpSel_Real_gfx10<0x373>;
1340 defm V_MAD_I32_I16 : VOP3OpSel_Real_gfx10<0x375>;
1343 VOP3OpSel_Real_gfx10_with_name<0x340, "V_MAD_U16_gfx9", "v_mad_u16">;
1345 VOP3OpSel_Real_gfx10_with_name<0x34b, "V_FMA_F16_gfx9", "v_fma_f16">;
1347 VOP3OpSel_Real_gfx10_with_name<0x35e, "V_MAD_I16_gfx9", "v_mad_i16">;
1349 VOP3OpSel_Real_gfx10_with_name<0x35f, "V_DIV_FIXUP_F16_gfx9", "v_div_fixup_f16">;
1351 defm V_ADD_NC_U16 : VOP3OpSel_Real_gfx10<0x303>;
1352 defm V_SUB_NC_U16 : VOP3OpSel_Real_gfx10<0x304>;
1356 defm V_MUL_LO_U16 : VOP3_Real_gfx10_with_name<0x305, "V_MUL_LO_U16", "v_mul_lo_u16">;
1357 defm V_LSHRREV_B16 : VOP3_Real_gfx10_with_name<0x307, "V_LSHRREV_B16", "v_lshrrev_b16">;
1358 defm V_ASHRREV_I16 : VOP3_Real_gfx10_with_name<0x308, "V_ASHRREV_I16", "v_ashrrev_i16">;
1359 defm V_MAX_U16 : VOP3_Real_gfx10_with_name<0x309, "V_MAX_U16", "v_max_u16">;
1360 defm V_MAX_I16 : VOP3_Real_gfx10_with_name<0x30a, "V_MAX_I16", "v_max_i16">;
1361 defm V_MIN_U16 : VOP3_Real_gfx10_with_name<0x30b, "V_MIN_U16", "v_min_u16">;
1362 defm V_MIN_I16 : VOP3_Real_gfx10_with_name<0x30c, "V_MIN_I16", "v_min_i16">;
1363 defm V_LSHLREV_B16 : VOP3_Real_gfx10_with_name<0x314, "V_LSHLREV_B16", "v_lshlrev_b16">;
1364 defm V_PERMLANE16_B32 : VOP3OpSel_Real_gfx10<0x377>;
1365 defm V_PERMLANEX16_B32 : VOP3OpSel_Real_gfx10<0x378>;
1375 VOP3e_gfx6_gfx7<op{8-0}, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl>;
1380 VOP3be_gfx6_gfx7<op{8-0}, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl>;
1390 defm V_QSAD_PK_U16_U8 : VOP3_Real_gfx7_gfx10<0x172>;
1391 defm V_MQSAD_U32_U8 : VOP3_Real_gfx7_gfx10<0x175>;
1392 defm V_MAD_U64_U32 : VOP3be_Real_gfx7_gfx10<0x176>;
1393 defm V_MAD_I64_I32 : VOP3be_Real_gfx7_gfx10<0x177>;
1403 VOP3e_gfx6_gfx7<op{8-0}, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl>;
1408 VOP3be_gfx6_gfx7<op{8-0}, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl>;
1418 defm V_LSHL_B64 : VOP3_Real_gfx6_gfx7<0x161>;
1419 defm V_LSHR_B64 : VOP3_Real_gfx6_gfx7<0x162>;
1420 defm V_ASHR_I64 : VOP3_Real_gfx6_gfx7<0x163>;
1421 defm V_MUL_LO_I32 : VOP3_Real_gfx6_gfx7<0x16b>;
1423 defm V_MAD_LEGACY_F32 : VOP3_Real_gfx6_gfx7_gfx10<0x140>;
1424 defm V_MAD_F32 : VOP3_Real_gfx6_gfx7_gfx10<0x141>;
1425 defm V_MAD_I32_I24 : VOP3_Real_gfx6_gfx7_gfx10<0x142>;
1426 defm V_MAD_U32_U24 : VOP3_Real_gfx6_gfx7_gfx10<0x143>;
1427 defm V_CUBEID_F32 : VOP3_Real_gfx6_gfx7_gfx10<0x144>;
1428 defm V_CUBESC_F32 : VOP3_Real_gfx6_gfx7_gfx10<0x145>;
1429 defm V_CUBETC_F32 : VOP3_Real_gfx6_gfx7_gfx10<0x146>;
1430 defm V_CUBEMA_F32 : VOP3_Real_gfx6_gfx7_gfx10<0x147>;
1431 defm V_BFE_U32 : VOP3_Real_gfx6_gfx7_gfx10<0x148>;
1432 defm V_BFE_I32 : VOP3_Real_gfx6_gfx7_gfx10<0x149>;
1433 defm V_BFI_B32 : VOP3_Real_gfx6_gfx7_gfx10<0x14a>;
1434 defm V_FMA_F32 : VOP3_Real_gfx6_gfx7_gfx10<0x14b>;
1435 defm V_FMA_F64 : VOP3_Real_gfx6_gfx7_gfx10<0x14c>;
1436 defm V_LERP_U8 : VOP3_Real_gfx6_gfx7_gfx10<0x14d>;
1437 defm V_ALIGNBIT_B32 : VOP3_Real_gfx6_gfx7_gfx10<0x14e>;
1438 defm V_ALIGNBYTE_B32 : VOP3_Real_gfx6_gfx7_gfx10<0x14f>;
1439 defm V_MULLIT_F32 : VOP3_Real_gfx6_gfx7_gfx10<0x150>;
1440 defm V_MIN3_F32 : VOP3_Real_gfx6_gfx7_gfx10<0x151>;
1441 defm V_MIN3_I32 : VOP3_Real_gfx6_gfx7_gfx10<0x152>;
1442 defm V_MIN3_U32 : VOP3_Real_gfx6_gfx7_gfx10<0x153>;
1443 defm V_MAX3_F32 : VOP3_Real_gfx6_gfx7_gfx10<0x154>;
1444 defm V_MAX3_I32 : VOP3_Real_gfx6_gfx7_gfx10<0x155>;
1445 defm V_MAX3_U32 : VOP3_Real_gfx6_gfx7_gfx10<0x156>;
1446 defm V_MED3_F32 : VOP3_Real_gfx6_gfx7_gfx10<0x157>;
1447 defm V_MED3_I32 : VOP3_Real_gfx6_gfx7_gfx10<0x158>;
1448 defm V_MED3_U32 : VOP3_Real_gfx6_gfx7_gfx10<0x159>;
1449 defm V_SAD_U8 : VOP3_Real_gfx6_gfx7_gfx10<0x15a>;
1450 defm V_SAD_HI_U8 : VOP3_Real_gfx6_gfx7_gfx10<0x15b>;
1451 defm V_SAD_U16 : VOP3_Real_gfx6_gfx7_gfx10<0x15c>;
1452 defm V_SAD_U32 : VOP3_Real_gfx6_gfx7_gfx10<0x15d>;
1453 defm V_CVT_PK_U8_F32 : VOP3_Real_gfx6_gfx7_gfx10<0x15e>;
1454 defm V_DIV_FIXUP_F32 : VOP3_Real_gfx6_gfx7_gfx10<0x15f>;
1455 defm V_DIV_FIXUP_F64 : VOP3_Real_gfx6_gfx7_gfx10<0x160>;
1456 defm V_ADD_F64 : VOP3_Real_gfx6_gfx7_gfx10<0x164>;
1457 defm V_MUL_F64 : VOP3_Real_gfx6_gfx7_gfx10<0x165>;
1458 defm V_MIN_F64 : VOP3_Real_gfx6_gfx7_gfx10<0x166>;
1459 defm V_MAX_F64 : VOP3_Real_gfx6_gfx7_gfx10<0x167>;
1460 defm V_LDEXP_F64 : VOP3_Real_gfx6_gfx7_gfx10<0x168>;
1461 defm V_MUL_LO_U32 : VOP3_Real_gfx6_gfx7_gfx10<0x169>;
1462 defm V_MUL_HI_U32 : VOP3_Real_gfx6_gfx7_gfx10<0x16a>;
1463 defm V_MUL_HI_I32 : VOP3_Real_gfx6_gfx7_gfx10<0x16c>;
1464 defm V_DIV_FMAS_F32 : VOP3_Real_gfx6_gfx7_gfx10<0x16f>;
1465 defm V_DIV_FMAS_F64 : VOP3_Real_gfx6_gfx7_gfx10<0x170>;
1466 defm V_MSAD_U8 : VOP3_Real_gfx6_gfx7_gfx10<0x171>;
1467 defm V_MQSAD_PK_U16_U8 : VOP3_Real_gfx6_gfx7_gfx10<0x173>;
1468 defm V_TRIG_PREOP_F64 : VOP3_Real_gfx6_gfx7_gfx10<0x174>;
1469 defm V_DIV_SCALE_F32 : VOP3be_Real_gfx6_gfx7_gfx10<0x16d>;
1470 defm V_DIV_SCALE_F64 : VOP3be_Real_gfx6_gfx7_gfx10<0x16e>;
1474 defm V_FMA_LEGACY_F32 : VOP3_Real_gfx10<0x140>;
1565 defm V_MAD_U64_U32 : VOP3be_Real_vi <0x1E8>;
1566 defm V_MAD_I64_I32 : VOP3be_Real_vi <0x1E9>;
1568 defm V_MAD_LEGACY_F32 : VOP3_Real_vi <0x1c0>;
1569 defm V_MAD_F32 : VOP3_Real_vi <0x1c1>;
1570 defm V_MAD_I32_I24 : VOP3_Real_vi <0x1c2>;
1571 defm V_MAD_U32_U24 : VOP3_Real_vi <0x1c3>;
1572 defm V_CUBEID_F32 : VOP3_Real_vi <0x1c4>;
1573 defm V_CUBESC_F32 : VOP3_Real_vi <0x1c5>;
1574 defm V_CUBETC_F32 : VOP3_Real_vi <0x1c6>;
1575 defm V_CUBEMA_F32 : VOP3_Real_vi <0x1c7>;
1576 defm V_BFE_U32 : VOP3_Real_vi <0x1c8>;
1577 defm V_BFE_I32 : VOP3_Real_vi <0x1c9>;
1578 defm V_BFI_B32 : VOP3_Real_vi <0x1ca>;
1579 defm V_FMA_F32 : VOP3_Real_vi <0x1cb>;
1580 defm V_FMA_F64 : VOP3_Real_vi <0x1cc>;
1581 defm V_LERP_U8 : VOP3_Real_vi <0x1cd>;
1582 defm V_ALIGNBIT_B32 : VOP3_Real_vi <0x1ce>;
1583 defm V_ALIGNBYTE_B32 : VOP3_Real_vi <0x1cf>;
1584 defm V_MIN3_F32 : VOP3_Real_vi <0x1d0>;
1585 defm V_MIN3_I32 : VOP3_Real_vi <0x1d1>;
1586 defm V_MIN3_U32 : VOP3_Real_vi <0x1d2>;
1587 defm V_MAX3_F32 : VOP3_Real_vi <0x1d3>;
1588 defm V_MAX3_I32 : VOP3_Real_vi <0x1d4>;
1589 defm V_MAX3_U32 : VOP3_Real_vi <0x1d5>;
1590 defm V_MED3_F32 : VOP3_Real_vi <0x1d6>;
1591 defm V_MED3_I32 : VOP3_Real_vi <0x1d7>;
1592 defm V_MED3_U32 : VOP3_Real_vi <0x1d8>;
1593 defm V_SAD_U8 : VOP3_Real_vi <0x1d9>;
1594 defm V_SAD_HI_U8 : VOP3_Real_vi <0x1da>;
1595 defm V_SAD_U16 : VOP3_Real_vi <0x1db>;
1596 defm V_SAD_U32 : VOP3_Real_vi <0x1dc>;
1597 defm V_CVT_PK_U8_F32 : VOP3_Real_vi <0x1dd>;
1598 defm V_DIV_FIXUP_F32 : VOP3_Real_vi <0x1de>;
1599 defm V_DIV_FIXUP_F64 : VOP3_Real_vi <0x1df>;
1600 defm V_DIV_SCALE_F32 : VOP3be_Real_vi <0x1e0>;
1601 defm V_DIV_SCALE_F64 : VOP3be_Real_vi <0x1e1>;
1602 defm V_DIV_FMAS_F32 : VOP3_Real_vi <0x1e2>;
1603 defm V_DIV_FMAS_F64 : VOP3_Real_vi <0x1e3>;
1604 defm V_MSAD_U8 : VOP3_Real_vi <0x1e4>;
1605 defm V_QSAD_PK_U16_U8 : VOP3_Real_vi <0x1e5>;
1606 defm V_MQSAD_PK_U16_U8 : VOP3_Real_vi <0x1e6>;
1607 defm V_MQSAD_U32_U8 : VOP3_Real_vi <0x1e7>;
1609 defm V_PERM_B32 : VOP3_Real_vi <0x1ed>;
1611 defm V_MAD_F16 : VOP3_F16_Real_vi <0x1ea>;
1612 defm V_MAD_U16 : VOP3_F16_Real_vi <0x1eb>;
1613 defm V_MAD_I16 : VOP3_F16_Real_vi <0x1ec>;
1614 defm V_FMA_F16 : VOP3_F16_Real_vi <0x1ee>;
1615 defm V_DIV_FIXUP_F16 : VOP3_F16_Real_vi <0x1ef>;
1616 defm V_INTERP_P2_F16 : VOP3Interp_F16_Real_vi <0x276>;
1619 defm V_MAD_LEGACY_F16 : VOP3_F16_Real_gfx9 <0x1ea, "V_MAD_F16", "v_mad_legacy_f16">;
1620 defm V_FMA_LEGACY_F16 : VOP3_F16_Real_gfx9 <0x1ee, "V_FMA_F16", "v_fma_legacy_f16">;
1621 defm V_DIV_FIXUP_LEGACY_F16 : VOP3_F16_Real_gfx9 <0x1ef, "V_DIV_FIXUP_F16", "v_div_fixup_legacy_f16…
1622 defm V_INTERP_P2_LEGACY_F16 : VOP3Interp_F16_Real_gfx9 <0x276, "V_INTERP_P2_F16", "v_interp_p2_lega…
1625 defm V_MAD_LEGACY_U16 : VOP3_F16_Real_gfx9 <0x1eb, "V_MAD_U16", "v_mad_legacy_u16">;
1626 defm V_MAD_LEGACY_I16 : VOP3_F16_Real_gfx9 <0x1ec, "V_MAD_I16", "v_mad_legacy_i16">;
1628 defm V_MAD_F16_gfx9 : VOP3OpSel_F16_Real_gfx9 <0x203, "v_mad_f16">;
1629 defm V_MAD_U16_gfx9 : VOP3OpSel_F16_Real_gfx9 <0x204, "v_mad_u16">;
1630 defm V_MAD_I16_gfx9 : VOP3OpSel_F16_Real_gfx9 <0x205, "v_mad_i16">;
1631 defm V_FMA_F16_gfx9 : VOP3OpSel_F16_Real_gfx9 <0x206, "v_fma_f16">;
1632 defm V_DIV_FIXUP_F16_gfx9 : VOP3OpSel_F16_Real_gfx9 <0x207, "v_div_fixup_f16">;
1633 defm V_INTERP_P2_F16_gfx9 : VOP3Interp_F16_Real_gfx9 <0x277, "V_INTERP_P2_F16_gfx9", "v_interp_p2…
1635 defm V_ADD_I32 : VOP3_Real_vi <0x29c>;
1636 defm V_SUB_I32 : VOP3_Real_vi <0x29d>;
1638 defm V_INTERP_P1_F32_e64 : VOP3Interp_Real_vi <0x270>;
1639 defm V_INTERP_P2_F32_e64 : VOP3Interp_Real_vi <0x271>;
1640 defm V_INTERP_MOV_F32_e64 : VOP3Interp_Real_vi <0x272>;
1642 defm V_INTERP_P1LL_F16 : VOP3Interp_Real_vi <0x274>;
1643 defm V_INTERP_P1LV_F16 : VOP3Interp_Real_vi <0x275>;
1644 defm V_ADD_F64 : VOP3_Real_vi <0x280>;
1645 defm V_MUL_F64 : VOP3_Real_vi <0x281>;
1646 defm V_MIN_F64 : VOP3_Real_vi <0x282>;
1647 defm V_MAX_F64 : VOP3_Real_vi <0x283>;
1648 defm V_LDEXP_F64 : VOP3_Real_vi <0x284>;
1649 defm V_MUL_LO_U32 : VOP3_Real_vi <0x285>;
1653 defm V_MUL_LO_I32 : VOP3_Real_vi <0x285>;
1656 defm V_MUL_HI_U32 : VOP3_Real_vi <0x286>;
1657 defm V_MUL_HI_I32 : VOP3_Real_vi <0x287>;
1659 defm V_READLANE_B32 : VOP3_Real_No_Suffix_vi <0x289>;
1660 defm V_WRITELANE_B32 : VOP3_Real_No_Suffix_vi <0x28a>;
1662 defm V_LSHLREV_B64 : VOP3_Real_vi <0x28f>;
1663 defm V_LSHRREV_B64 : VOP3_Real_vi <0x290>;
1664 defm V_ASHRREV_I64 : VOP3_Real_vi <0x291>;
1665 defm V_TRIG_PREOP_F64 : VOP3_Real_vi <0x292>;
1667 defm V_LSHL_ADD_U32 : VOP3_Real_vi <0x1fd>;
1668 defm V_ADD_LSHL_U32 : VOP3_Real_vi <0x1fe>;
1669 defm V_ADD3_U32 : VOP3_Real_vi <0x1ff>;
1670 defm V_LSHL_OR_B32 : VOP3_Real_vi <0x200>;
1671 defm V_AND_OR_B32 : VOP3_Real_vi <0x201>;
1672 defm V_OR3_B32 : VOP3_Real_vi <0x202>;
1673 defm V_PACK_B32_F16 : VOP3OpSel_Real_gfx9 <0x2a0>;
1675 defm V_XAD_U32 : VOP3_Real_vi <0x1f3>;
1677 defm V_MIN3_F16 : VOP3OpSel_Real_gfx9 <0x1f4>;
1678 defm V_MIN3_I16 : VOP3OpSel_Real_gfx9 <0x1f5>;
1679 defm V_MIN3_U16 : VOP3OpSel_Real_gfx9 <0x1f6>;
1681 defm V_MAX3_F16 : VOP3OpSel_Real_gfx9 <0x1f7>;
1682 defm V_MAX3_I16 : VOP3OpSel_Real_gfx9 <0x1f8>;
1683 defm V_MAX3_U16 : VOP3OpSel_Real_gfx9 <0x1f9>;
1685 defm V_MED3_F16 : VOP3OpSel_Real_gfx9 <0x1fa>;
1686 defm V_MED3_I16 : VOP3OpSel_Real_gfx9 <0x1fb>;
1687 defm V_MED3_U16 : VOP3OpSel_Real_gfx9 <0x1fc>;
1689 defm V_ADD_I16 : VOP3OpSel_Real_gfx9 <0x29e>;
1690 defm V_SUB_I16 : VOP3OpSel_Real_gfx9 <0x29f>;
1692 defm V_MAD_U32_U16 : VOP3OpSel_Real_gfx9 <0x1f1>;
1693 defm V_MAD_I32_I16 : VOP3OpSel_Real_gfx9 <0x1f2>;
1695 defm V_CVT_PKNORM_I16_F16 : VOP3OpSel_Real_gfx9 <0x299>;
1696 defm V_CVT_PKNORM_U16_F16 : VOP3OpSel_Real_gfx9 <0x29a>;
1698 defm V_LSHL_ADD_U64 : VOP3_Real_vi <0x208>;
1700 defm V_CVT_PK_FP8_F32 : VOP3OpSel_Real_gfx9 <0x2a2>;
1701 defm V_CVT_PK_BF8_F32 : VOP3OpSel_Real_gfx9 <0x2a3>;
1702 defm V_CVT_SR_FP8_F32 : VOP3OpSel_Real_gfx9_forced_opsel2 <0x2a4>;
1703 defm V_CVT_SR_BF8_F32 : VOP3OpSel_Real_gfx9_forced_opsel2 <0x2a5>;