Lines Matching refs:Gen
93 class VOP1_Real_Gen <VOP1_Pseudo ps, GFXGen Gen, string real_name = ps.Mnemonic> :
94 VOP1_Real <ps, Gen.Subtarget, real_name> {
95 let AssemblerPredicate = Gen.AssemblerPredicate;
96 let DecoderNamespace = Gen.DecoderNamespace;
778 class VOP1_DPP16_Gen<bits<8> op, VOP1_DPP_Pseudo ps, GFXGen Gen, VOPProfile p = ps.Pfl> :
779 VOP1_DPP16 <op, ps, Gen.Subtarget, p> {
780 let AssemblerPredicate = Gen.AssemblerPredicate;
781 let DecoderNamespace = Gen.DecoderNamespace;
800 class VOP1_DPP8_Gen<bits<8> op, VOP1_Pseudo ps, GFXGen Gen, VOPProfile p = ps.Pfl> :
802 let AssemblerPredicate = Gen.AssemblerPredicate;
803 let DecoderNamespace = Gen.DecoderNamespace;
810 multiclass VOP1Only_Real<GFXGen Gen, bits<9> op> {
812 def Gen.Suffix :
813 VOP1_Real_Gen<!cast<VOP1_Pseudo>(NAME), Gen>,
817 multiclass VOP1_Real_e32<GFXGen Gen, bits<9> op, string opName = NAME> {
819 def _e32#Gen.Suffix :
820 VOP1_Real_Gen<ps, Gen>,
824 multiclass VOP1_Real_e32_with_name<GFXGen Gen, bits<9> op, string opName,
828 DecoderNamespace = Gen.DecoderNamespace #
830 defm NAME : VOP1_Real_e32<Gen, op, opName>;
834 multiclass VOP1_Real_e64<GFXGen Gen, bits<9> op> {
835 def _e64#Gen.Suffix :
836 VOP3_Real_Gen<!cast<VOP3_Pseudo>(NAME#"_e64"), Gen>,
840 multiclass VOP1_Real_dpp<GFXGen Gen, bits<9> op, string opName = NAME> {
842 def _dpp#Gen.Suffix : VOP1_DPP16_Gen<op{7-0}, !cast<VOP1_DPP_Pseudo>(opName#"_dpp"), Gen>;
845 multiclass VOP1_Real_dpp_with_name<GFXGen Gen, bits<9> op, string opName,
849 DecoderNamespace = Gen.DecoderNamespace #
851 defm NAME : VOP1_Real_dpp<Gen, op, opName>;
855 multiclass VOP1_Real_dpp8<GFXGen Gen, bits<9> op, string opName = NAME> {
857 def _dpp8#Gen.Suffix : VOP1_DPP8_Gen<op{7-0}, ps, Gen>;
860 multiclass VOP1_Real_dpp8_with_name<GFXGen Gen, bits<9> op, string opName,
864 DecoderNamespace = Gen.DecoderNamespace #
866 defm NAME : VOP1_Real_dpp8<Gen, op, opName>;
870 multiclass VOP1_Realtriple_e64<GFXGen Gen, bits<9> op> {
871 defm NAME : VOP3_Realtriple<Gen, {0, 1, 1, op{6-0}}, /*isSingle=*/ 0, NAME>;
874 multiclass VOP1_Realtriple_e64_with_name<GFXGen Gen, bits<9> op, string opName,
876 defm NAME : VOP3_Realtriple_with_name<Gen, {0, 1, 1, op{6-0}}, opName,
880 multiclass VOP1_Real_FULL<GFXGen Gen, bits<9> op> :
881 VOP1_Real_e32<Gen, op>, VOP1_Realtriple_e64<Gen, op>,
882 VOP1_Real_dpp<Gen, op>, VOP1_Real_dpp8<Gen, op>;
902 multiclass VOP1_Real_FULL_with_name<GFXGen Gen, bits<9> op, string opName,
904 VOP1_Real_e32_with_name<Gen, op, opName, asmName>,
905 VOP1_Real_dpp_with_name<Gen, op, opName, asmName>,
906 VOP1_Real_dpp8_with_name<Gen, op, opName, asmName>,
907 VOP1_Realtriple_e64_with_name<Gen, op, opName, asmName>;
909 multiclass VOP1_Real_NO_DPP<GFXGen Gen, bits<9> op> :
910 VOP1_Real_e32<Gen, op>, VOP1_Real_e64<Gen, op>;
928 multiclass VOP1_Real_NO_DPP_OP_SEL_with_name<GFXGen Gen, bits<9> op,
930 VOP1_Real_e32_with_name<Gen, op, opName, asmName>,
931 VOP3_Real_with_name<Gen, {0, 1, 1, op{6-0}}, opName, asmName>;