Lines Matching +full:op +full:- +full:mode
1 //===-- SOPInstructions.td - SOP Instruction Definitions ------------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
26 //===----------------------------------------------------------------------===//
28 //===----------------------------------------------------------------------===//
46 class SOP1_Real<bits<8> op, SOP1_Pseudo ps, string real_name = ps.Mnemonic> :
57 // copy relevant pseudo op flags
75 let Inst{7-0} = !if(ps.has_src0, src0, ?);
76 let Inst{15-8} = op;
77 let Inst{22-16} = !if(ps.has_sdst, sdst, ?);
78 let Inst{31-23} = 0x17d; //encoding;
94 // 32-bit input, no output.
129 // 64-bit input, 32-bit output.
135 // 32-bit input, 64-bit output.
144 // no input, 64-bit output.
150 // 64-bit input, no output
157 class UniformUnaryFrag<SDPatternOperator Op> : PatFrag <
159 (Op $src0),
160 [{ return !N->isDivergent(); }]> {
169 class UniformBinFrag<SDPatternOperator Op> : PatFrag <
171 (Op $src0, $src1),
172 [{ return !N->isDivergent(); }]> {
181 class UniformTernaryFrag<SDPatternOperator Op> : PatFrag <
183 (Op $src0, $src1, $src2),
184 [{ return !N->isDivergent(); }]> {
193 class DivergentBinFrag<SDPatternOperator Op> : PatFrag <
195 (Op $src0, $src1),
196 [{ return N->isDivergent(); }]> {
309 // zero-extend the result from 48 bits instead of sign-extending.
371 let Uses = [M0, MODE];
372 let Defs = [M0, MODE];
425 class SOP1_F32_Inst<string opName, SDPatternOperator Op, ValueType vt0=f32,
427 SOP1_32<opName, [(set vt0:$sdst, (UniformUnaryFrag<Op> vt1:$src0))]>;
429 let SubtargetPredicate = HasSALUFloatInsts, Uses = [MODE],
453 } // End SubtargetPredicate = HasSALUFloatInsts, Uses = [MODE]
537 //===----------------------------------------------------------------------===//
539 //===----------------------------------------------------------------------===//
570 // copy relevant pseudo op flags
590 class SOP2_Real32<bits<7> op, SOP_Pseudo ps, string name = ps.Mnemonic> :
592 let Inst{7-0} = src0;
593 let Inst{15-8} = src1;
594 let Inst{22-16} = !if(ps.has_sdst, sdst, ?);
595 let Inst{29-23} = op;
596 let Inst{31-30} = 0x2; // encoding
599 class SOP2_Real64<bits<7> op, SOP_Pseudo ps, string name = ps.Mnemonic> :
601 let Inst{7-0} = src0;
602 let Inst{15-8} = src1;
603 let Inst{22-16} = !if(ps.has_sdst, sdst, ?);
604 let Inst{29-23} = op;
605 let Inst{31-30} = 0x2; // encoding
606 let Inst{63-32} = imm;
691 // The higher 32-bits of the inputs contain the sign extension bits.
696 // The higher 32-bits of the inputs are zero.
879 class SOP2_F32_Inst<string opName, SDPatternOperator Op, ValueType dstVt=f32> :
881 [(set dstVt:$sdst, (UniformBinFrag<Op> SSrc_f32:$src0, SSrc_f32:$src1))]>;
883 class SOP2_F16_Inst<string opName, SDPatternOperator Op> :
885 [(set f16:$sdst, (UniformBinFrag<Op> SSrc_f16:$src0, SSrc_f16:$src1))]>;
888 Uses = [MODE], SchedRW = [WriteSFPU] in {
945 // Uses = [MODE], SchedRW = [WriteSFPU]
947 // On GFX12 MIN/MAX instructions do not read MODE register.
956 //===----------------------------------------------------------------------===//
958 //===----------------------------------------------------------------------===//
984 // copy relevant pseudo op flags
1006 class SOPK_Real32<bits<5> op, SOPK_Pseudo ps, string name = ps.Mnemonic> :
1009 let Inst{15-0} = simm16;
1010 let Inst{22-16} = !if(ps.has_sdst, sdst, ?);
1011 let Inst{27-23} = op;
1012 let Inst{31-28} = 0xb; //encoding
1015 class SOPK_Real64<bits<5> op, SOPK_Pseudo ps> :
1018 let Inst{15-0} = simm16;
1019 let Inst{22-16} = !if(ps.has_sdst, sdst, ?);
1020 let Inst{27-23} = op;
1021 let Inst{31-28} = 0xb; //encoding
1022 let Inst{63-32} = imm;
1123 // FIXME: Need to truncate immediate to 16-bits.
1124 // FIXME: Should have separate pseudos for known may read MODE and
1125 // only read MODE.
1132 let Uses = [MODE];
1135 let Defs = [MODE], Uses = [MODE] in {
1137 // FIXME: Need to truncate immediate to 16-bits.
1152 // Variant of SETREG that is guaranteed to only touch FP bits in the MODE
1173 // Variant of SETREG_IMM32 that is guaranteed to only touch FP bits in the MODE
1179 } // End Defs = [MODE], Uses = [MODE]
1228 //===----------------------------------------------------------------------===//
1230 //===----------------------------------------------------------------------===//
1245 class SOPC_Real<bits<7> op, SOPC_Pseudo ps> :
1254 // copy relevant pseudo op flags
1270 let Inst{7-0} = src0;
1271 let Inst{15-8} = src1;
1272 let Inst{22-16} = op;
1273 let Inst{31-23} = 0x17e;
1305 let Uses = [MODE];
1317 let Uses = [MODE];
1361 // Setting the GPR index mode is really writing the fields in the mode
1362 // register. We don't want to add mode register uses to every
1370 let Defs = [M0, MODE]; // No scc def
1371 let Uses = [M0, MODE]; // Other bits of mode, m0 unmodified.
1372 let hasSideEffects = 1; // Sets mode.gpr_idx_en
1411 //===----------------------------------------------------------------------===//
1413 //===----------------------------------------------------------------------===//
1446 // copy relevant pseudo op flags
1465 class SOPP_Real_32 <bits<7> op, SOPP_Pseudo ps, string name = ps.Mnemonic> : SOPP_Real<ps, name>,
1467 let Inst{15-0} = !if(ps.fixed_imm, ps.simm16, simm16);
1468 let Inst{22-16} = op;
1469 let Inst{31-23} = 0x17f;
1472 class SOPP_Real_64 <bits<7> op, SOPP_Pseudo ps, string name = ps.Mnemonic> : SOPP_Real<ps, name>,
1475 let Inst{15-0} = !if(ps.fixed_imm, ps.simm16, simm16);
1476 let Inst{22-16} = op;
1477 let Inst{31-23} = 0x17f;
1479 let Inst{47-32} = 0x0;
1480 let Inst{54-48} = 0x0;
1481 let Inst{63-55} = 0x17f;
1622 // "_soft" waitcnts are waitcnts that are either relaxed into their non-soft
1699 let Defs = [MODE];
1700 let Uses = [MODE];
1708 let Defs = [M0, MODE];
1709 let Uses = [MODE];
1726 let hasSideEffects = 0, Uses = [MODE], Defs = [MODE] in {
1786 //===----------------------------------------------------------------------===//
1788 //===----------------------------------------------------------------------===//
1817 // Same as a 32-bit inreg
1828 // The first 10 bits of the mode register are the core FP mode on all
1832 // non-floating point environment information. We extract the full
1833 // register and clear non-relevant bits.
1836 // non-FP exceptions.
1838 // Bits 12-18 cover the relevant exception mask on all subtargets.
1844 // Bit 23 is the additional FP16_OVFL mode.
1846 // Bits 19, 20, and 21 cover non-FP exceptions and differ between
1852 defvar fp_round_mask = !add(!shl(1, 4), -1);
1853 defvar fp_denorm_mask = !shl(!add(!shl(1, 4), -1), 4);
1861 defvar fp_excp_en_mask = !shl(!add(!shl(1, 7), -1), 12);
1870 HWREG.MODE, 0,
1876 // care about the rounding or denorm mode bits. We also can reduce the
1894 //===----------------------------------------------------------------------===//
1896 //===----------------------------------------------------------------------===//
1901 [{ return !N->isDivergent(); }]
1920 // case, the sgpr-copies pass will fix this to use the vector version.
1926 // FIXME: We need to use COPY_TO_REGCLASS to work-around the fact that
1947 class ScalarNot2Pat<Instruction inst, SDPatternOperator op, ValueType vt,
1949 (UniformBinFrag<op> vt:$src0, (notnode vt:$src1)),
1965 //===----------------------------------------------------------------------===//
1966 // Target-specific instruction encodings.
1967 //===----------------------------------------------------------------------===//
1984 //===----------------------------------------------------------------------===//
1985 // SOP1 - GFX11, GFX12
1986 //===----------------------------------------------------------------------===//
1988 multiclass SOP1_Real_gfx11<bits<8> op, string name = !tolower(NAME)> {
1990 def _gfx11 : SOP1_Real<op, ps, name>,
1998 multiclass SOP1_Real_gfx12<bits<8> op, string name = !tolower(NAME)> {
2000 def _gfx12 : SOP1_Real<op, ps, name>,
2008 multiclass SOP1_M0_Real_gfx12<bits<8> op> {
2009 def _gfx12 : SOP1_Real<op, !cast<SOP1_Pseudo>(NAME)>,
2011 let Inst{7-0} = M0_gfx11plus.HWEncoding{7-0}; // Set Src0 encoding to M0
2015 multiclass SOP1_IMM_Real_gfx12<bits<8> op> {
2017 def _gfx12 : SOP1_Real<op, ps>,
2021 multiclass SOP1_Real_gfx11_gfx12<bits<8> op, string name = !tolower(NAME)> :
2022 SOP1_Real_gfx11<op, name>, SOP1_Real_gfx12<op, name>;
2102 //===----------------------------------------------------------------------===//
2103 // SOP1 - GFX1150, GFX12
2104 //===----------------------------------------------------------------------===//
2122 //===----------------------------------------------------------------------===//
2123 // SOP1 - GFX10.
2124 //===----------------------------------------------------------------------===//
2126 multiclass SOP1_Real_gfx10<bits<8> op> {
2128 def _gfx10 : SOP1_Real<op, ps>,
2132 multiclass SOP1_Real_gfx10_gfx11_gfx12<bits<8> op> :
2133 SOP1_Real_gfx10<op>, SOP1_Real_gfx11_gfx12<op>;
2154 //===----------------------------------------------------------------------===//
2155 // SOP1 - GFX6, GFX7, GFX10, GFX11.
2156 //===----------------------------------------------------------------------===//
2159 multiclass SOP1_Real_gfx6_gfx7<bits<8> op> {
2161 def _gfx6_gfx7 : SOP1_Real<op, ps>,
2165 multiclass SOP1_Real_gfx6_gfx7_gfx10<bits<8> op> :
2166 SOP1_Real_gfx6_gfx7<op>, SOP1_Real_gfx10<op>;
2168 multiclass SOP1_Real_gfx6_gfx7_gfx10_gfx11_gfx12<bits<8> op> :
2169 SOP1_Real_gfx6_gfx7<op>, SOP1_Real_gfx10_gfx11_gfx12<op>;
2221 //===----------------------------------------------------------------------===//
2222 // SOP2 - GFX12
2223 //===----------------------------------------------------------------------===//
2225 multiclass SOP2_Real_gfx12<bits<7> op, string name = !tolower(NAME)> {
2227 def _gfx12 : SOP2_Real32<op, ps, name>,
2240 //===----------------------------------------------------------------------===//
2241 // SOP2 - GFX11, GFX12.
2242 //===----------------------------------------------------------------------===//
2244 multiclass SOP2_Real_gfx11<bits<7> op, string name = !tolower(NAME)> {
2246 def _gfx11 : SOP2_Real32<op, ps, name>,
2254 multiclass SOP2_Real_gfx11_gfx12<bits<7> op, string name = !tolower(NAME)> :
2255 SOP2_Real_gfx11<op, name>, SOP2_Real_gfx12<op, name>;
2304 //===----------------------------------------------------------------------===//
2305 // SOP2 - GFX1150, GFX12
2306 //===----------------------------------------------------------------------===//
2308 multiclass SOP2_Real_FMAK_gfx12<bits<7> op> {
2309 def _gfx12 : SOP2_Real64<op, !cast<SOP2_Pseudo>(NAME)>,
2313 multiclass SOP2_Real_FMAK_gfx11<bits<7> op> {
2314 def _gfx11 : SOP2_Real64<op, !cast<SOP2_Pseudo>(NAME)>,
2318 multiclass SOP2_Real_FMAK_gfx11_gfx12<bits<7> op> :
2319 SOP2_Real_FMAK_gfx11<op>, SOP2_Real_FMAK_gfx12<op>;
2333 //===----------------------------------------------------------------------===//
2334 // SOP2 - GFX1150
2335 //===----------------------------------------------------------------------===//
2337 multiclass SOP2_Real_gfx11_Renamed_gfx12<bits<7> op, string gfx12_name> :
2338 SOP2_Real_gfx11<op>, SOP2_Real_gfx12<op, gfx12_name>;
2345 //===----------------------------------------------------------------------===//
2346 // SOP2 - GFX10.
2347 //===----------------------------------------------------------------------===//
2349 multiclass SOP2_Real_gfx10<bits<7> op> {
2351 def _gfx10 : SOP2_Real32<op, ps>,
2355 multiclass SOP2_Real_gfx10_gfx11_gfx12<bits<7> op> :
2356 SOP2_Real_gfx10<op>, SOP2_Real_gfx11_gfx12<op>;
2368 //===----------------------------------------------------------------------===//
2369 // SOP2 - GFX6, GFX7.
2370 //===----------------------------------------------------------------------===//
2372 multiclass SOP2_Real_gfx6_gfx7<bits<7> op> {
2374 def _gfx6_gfx7 : SOP2_Real32<op, ps>,
2378 multiclass SOP2_Real_gfx6_gfx7_gfx10<bits<7> op> :
2379 SOP2_Real_gfx6_gfx7<op>, SOP2_Real_gfx10<op>;
2381 multiclass SOP2_Real_gfx6_gfx7_gfx10_gfx11_Renamed_gfx12<bits<7> op, string gfx12_name> :
2382 SOP2_Real_gfx6_gfx7<op>, SOP2_Real_gfx10<op>, SOP2_Real_gfx11<op>,
2383 SOP2_Real_gfx12<op, gfx12_name>;
2430 //===----------------------------------------------------------------------===//
2431 // SOPK - GFX11, GFX12.
2432 //===----------------------------------------------------------------------===//
2434 multiclass SOPK_Real32_gfx12<bits<5> op, string name = !tolower(NAME)> {
2436 def _gfx12 : SOPK_Real32<op, ps, name>,
2444 multiclass SOPK_Real32_gfx11<bits<5> op> {
2445 def _gfx11 : SOPK_Real32<op, !cast<SOPK_Pseudo>(NAME)>,
2449 multiclass SOPK_Real64_gfx12<bits<5> op> {
2450 def _gfx12 : SOPK_Real64<op, !cast<SOPK_Pseudo>(NAME)>,
2454 multiclass SOPK_Real64_gfx11<bits<5> op> {
2455 def _gfx11 : SOPK_Real64<op, !cast<SOPK_Pseudo>(NAME)>,
2459 multiclass SOPK_Real32_gfx11_gfx12<bits<5> op> :
2460 SOPK_Real32_gfx11<op>, SOPK_Real32_gfx12<op>;
2462 multiclass SOPK_Real64_gfx11_gfx12<bits<5> op> :
2463 SOPK_Real64_gfx11<op>, SOPK_Real64_gfx12<op>;
2476 //===----------------------------------------------------------------------===//
2477 // SOPK - GFX10.
2478 //===----------------------------------------------------------------------===//
2480 multiclass SOPK_Real32_gfx10<bits<5> op> {
2482 def _gfx10 : SOPK_Real32<op, ps>,
2486 multiclass SOPK_Real64_gfx10<bits<5> op> {
2488 def _gfx10 : SOPK_Real64<op, ps>,
2492 multiclass SOPK_Real32_gfx10_gfx11<bits<5> op> :
2493 SOPK_Real32_gfx10<op>, SOPK_Real32_gfx11<op>;
2495 multiclass SOPK_Real32_gfx10_gfx11_gfx12<bits<5> op> :
2496 SOPK_Real32_gfx10<op>, SOPK_Real32_gfx11_gfx12<op>;
2507 //===----------------------------------------------------------------------===//
2508 // SOPK - GFX6, GFX7.
2509 //===----------------------------------------------------------------------===//
2511 multiclass SOPK_Real32_gfx6_gfx7<bits<5> op> {
2513 def _gfx6_gfx7 : SOPK_Real32<op, ps>,
2517 multiclass SOPK_Real64_gfx6_gfx7<bits<5> op> {
2519 def _gfx6_gfx7 : SOPK_Real64<op, ps>,
2523 multiclass SOPK_Real32_gfx6_gfx7_gfx10<bits<5> op> :
2524 SOPK_Real32_gfx6_gfx7<op>, SOPK_Real32_gfx10<op>;
2526 multiclass SOPK_Real64_gfx6_gfx7_gfx10<bits<5> op> :
2527 SOPK_Real64_gfx6_gfx7<op>, SOPK_Real64_gfx10<op>;
2529 multiclass SOPK_Real32_gfx6_gfx7_gfx10_gfx11<bits<5> op> :
2530 SOPK_Real32_gfx6_gfx7<op>, SOPK_Real32_gfx10_gfx11<op>;
2532 multiclass SOPK_Real32_gfx6_gfx7_gfx10_gfx11_gfx12<bits<5> op> :
2533 SOPK_Real32_gfx6_gfx7<op>, SOPK_Real32_gfx10_gfx11_gfx12<op>;
2535 multiclass SOPK_Real32_gfx6_gfx7_gfx10_gfx11_Renamed_gfx12<bits<5> op, string gfx12_name> :
2536 SOPK_Real32_gfx6_gfx7<op>, SOPK_Real32_gfx10<op>, SOPK_Real32_gfx11<op>,
2537 SOPK_Real32_gfx12<op, gfx12_name>;
2561 //===----------------------------------------------------------------------===//
2562 // SOPP - GFX12 only.
2563 //===----------------------------------------------------------------------===//
2565 multiclass SOPP_Real_32_gfx12<bits<7> op, string name = !tolower(NAME)> {
2567 def _gfx12 : SOPP_Real_32<op, ps, name>,
2587 //===----------------------------------------------------------------------===//
2588 // SOPP - GFX11, GFX12.
2589 //===----------------------------------------------------------------------===//
2592 multiclass SOPP_Real_32_gfx11<bits<7> op, string name = !tolower(NAME)> {
2594 def _gfx11 : SOPP_Real_32<op, ps, name>,
2603 multiclass SOPP_Real_64_gfx12<bits<7> op> {
2604 def _gfx12 : SOPP_Real_64<op, !cast<SOPP_Pseudo>(NAME), !cast<SOPP_Pseudo>(NAME).Mnemonic>,
2609 multiclass SOPP_Real_64_gfx11<bits<7> op> {
2610 def _gfx11 : SOPP_Real_64<op, !cast<SOPP_Pseudo>(NAME), !cast<SOPP_Pseudo>(NAME).Mnemonic>,
2615 multiclass SOPP_Real_32_gfx11_gfx12<bits<7> op> :
2616 SOPP_Real_32_gfx11<op>, SOPP_Real_32_gfx12<op>;
2618 multiclass SOPP_Real_32_gfx11_Renamed_gfx12<bits<7> op, string gfx12_name> :
2619 SOPP_Real_32_gfx11<op>, SOPP_Real_32_gfx12<op, gfx12_name>;
2621 multiclass SOPP_Real_With_Relaxation_gfx12<bits<7> op> {
2622 defm "" : SOPP_Real_32_gfx12<op>;
2624 defm _pad_s_nop : SOPP_Real_64_gfx12<op>;
2627 multiclass SOPP_Real_With_Relaxation_gfx11<bits<7> op> {
2628 defm "" : SOPP_Real_32_gfx11<op>;
2630 defm _pad_s_nop : SOPP_Real_64_gfx11<op>;
2633 multiclass SOPP_Real_With_Relaxation_gfx11_gfx12<bits<7>op> :
2634 SOPP_Real_With_Relaxation_gfx11<op>, SOPP_Real_With_Relaxation_gfx12<op>;
2674 //===----------------------------------------------------------------------===//
2675 // SOPP - GFX1150, GFX12.
2676 //===----------------------------------------------------------------------===//
2680 //===----------------------------------------------------------------------===//
2681 // SOPP - GFX6, GFX7, GFX8, GFX9, GFX10
2682 //===----------------------------------------------------------------------===//
2684 multiclass SOPP_Real_32_gfx6_gfx7<bits<7> op> {
2686 def _gfx6_gfx7 : SOPP_Real_32<op, ps, !cast<SOPP_Pseudo>(NAME).Mnemonic>,
2691 multiclass SOPP_Real_32_gfx8_gfx9<bits<7> op> {
2693 def _vi : SOPP_Real_32<op, ps>,
2698 multiclass SOPP_Real_32_gfx10<bits<7> op> {
2700 def _gfx10 : SOPP_Real_32<op, ps>,
2705 multiclass SOPP_Real_32_gfx8_gfx9_gfx10<bits<7> op> :
2706 SOPP_Real_32_gfx8_gfx9<op>, SOPP_Real_32_gfx10<op>;
2708 multiclass SOPP_Real_32_gfx6_gfx7_gfx8_gfx9<bits<7> op> :
2709 SOPP_Real_32_gfx6_gfx7<op>, SOPP_Real_32_gfx8_gfx9<op>;
2711 multiclass SOPP_Real_32_gfx6_gfx7_gfx8_gfx9_gfx10<bits<7> op> :
2712 SOPP_Real_32_gfx6_gfx7_gfx8_gfx9<op>, SOPP_Real_32_gfx10<op>;
2714 multiclass SOPP_Real_32_gfx6_gfx7_gfx8_gfx9_gfx10_gfx11_gfx12<bits<7> op> :
2715 SOPP_Real_32_gfx6_gfx7_gfx8_gfx9_gfx10<op>, SOPP_Real_32_gfx11_gfx12<op>;
2717 multiclass SOPP_Real_32_gfx10_gfx11_gfx12<bits<7> op> :
2718 SOPP_Real_32_gfx10<op>, SOPP_Real_32_gfx11_gfx12<op>;
2721 multiclass SOPP_Real_64_gfx6_gfx7<bits<7> op> {
2723 def _gfx6_gfx7 : SOPP_Real_64<op, ps>,
2728 multiclass SOPP_Real_64_gfx8_gfx9<bits<7> op> {
2730 def _vi : SOPP_Real_64<op, ps>,
2735 multiclass SOPP_Real_64_gfx10<bits<7> op> {
2737 def _gfx10 : SOPP_Real_64<op, ps>,
2742 multiclass SOPP_Real_64_gfx6_gfx7_gfx8_gfx9<bits<7> op> :
2743 SOPP_Real_64_gfx6_gfx7<op>, SOPP_Real_64_gfx8_gfx9<op>;
2745 multiclass SOPP_Real_64_gfx6_gfx7_gfx8_gfx9_gfx10<bits<7> op> :
2746 SOPP_Real_64_gfx6_gfx7_gfx8_gfx9<op>, SOPP_Real_64_gfx10<op>;
2749 multiclass SOPP_Real_With_Relaxation_gfx6_gfx7_gfx8_gfx9_gfx10<bits<7> op> {
2750 defm "" : SOPP_Real_32_gfx6_gfx7_gfx8_gfx9_gfx10<op>;
2752 defm _pad_s_nop : SOPP_Real_64_gfx6_gfx7_gfx8_gfx9_gfx10<op>;
2798 //===----------------------------------------------------------------------===//
2799 // SOPC - GFX11, GFX12.
2800 //===----------------------------------------------------------------------===//
2802 multiclass SOPC_Real_gfx12<bits<7> op> {
2803 def _gfx12 : SOPC_Real<op, !cast<SOPC_Pseudo>(NAME)>,
2807 multiclass SOPC_Real_gfx11<bits<7> op> {
2808 def _gfx11 : SOPC_Real<op, !cast<SOPC_Pseudo>(NAME)>,
2812 multiclass SOPC_Real_gfx11_gfx12<bits<7> op> :
2813 SOPC_Real_gfx11<op>, SOPC_Real_gfx12<op>;
2818 //===----------------------------------------------------------------------===//
2819 // SOPC - GFX1150, GFX12
2820 //===----------------------------------------------------------------------===//
2852 //===----------------------------------------------------------------------===//
2853 // SOPC - GFX6, GFX7, GFX8, GFX9, GFX10
2854 //===----------------------------------------------------------------------===//
2856 multiclass SOPC_Real_gfx6_gfx7<bits<7> op> {
2858 def _gfx6_gfx7 : SOPC_Real<op, ps>,
2862 multiclass SOPC_Real_gfx8_gfx9<bits<7> op> {
2864 def _vi : SOPC_Real<op, ps>,
2868 multiclass SOPC_Real_gfx10<bits<7> op> {
2870 def _gfx10 : SOPC_Real<op, ps>,
2874 multiclass SOPC_Real_gfx8_gfx9_gfx10<bits<7> op> :
2875 SOPC_Real_gfx8_gfx9<op>, SOPC_Real_gfx10<op>;
2877 multiclass SOPC_Real_gfx6_gfx7_gfx8_gfx9<bits<7> op> :
2878 SOPC_Real_gfx6_gfx7<op>, SOPC_Real_gfx8_gfx9<op>;
2880 multiclass SOPC_Real_gfx6_gfx7_gfx8_gfx9_gfx10_gfx11_gfx12<bits<7> op> :
2881 SOPC_Real_gfx6_gfx7_gfx8_gfx9<op>, SOPC_Real_gfx10<op>, SOPC_Real_gfx11<op>,
2882 SOPC_Real_gfx12<op>;
2905 //===----------------------------------------------------------------------===//
2907 //===----------------------------------------------------------------------===//
2909 class SOP1_Real_vi<bits<8> op, SOP1_Pseudo ps> :
2910 SOP1_Real<op, ps>,
2913 class SOP2_Real_vi<bits<7> op, SOP2_Pseudo ps> :
2914 SOP2_Real32<op, ps>,
2917 class SOPK_Real_vi<bits<5> op, SOPK_Pseudo ps> :
2918 SOPK_Real32<op, ps>,
3044 //===----------------------------------------------------------------------===//
3045 // SOP1 - GFX9.
3046 //===----------------------------------------------------------------------===//
3054 //===----------------------------------------------------------------------===//
3055 // SOP2 - GFX9.
3056 //===----------------------------------------------------------------------===//