Lines Matching full:ps
53 class SM_Real <SM_Pseudo ps, string opName = ps.Mnemonic>
54 : InstSI<ps.OutOperandList, ps.InOperandList, opName # ps.AsmOperands> {
62 let LGKM_CNT = ps.LGKM_CNT;
63 let SMRD = ps.SMRD;
64 let mayStore = ps.mayStore;
65 let mayLoad = ps.mayLoad;
66 let hasSideEffects = ps.hasSideEffects;
67 let UseNamedOperandTable = ps.UseNamedOperandTable;
68 let SchedRW = ps.SchedRW;
69 let SubtargetPredicate = ps.SubtargetPredicate;
70 let OtherPredicates = ps.OtherPredicates;
71 let AsmMatchConverter = ps.AsmMatchConverter;
72 let IsAtomicRet = ps.IsAtomicRet;
73 let IsAtomicNoRet = ps.IsAtomicNoRet;
74 let Uses = ps.Uses;
75 let Defs = ps.Defs;
77 let TSFlags = ps.TSFlags;
79 bit is_buffer = ps.is_buffer;
482 class SMRD_Real_si <bits<5> op, SM_Pseudo ps>
483 : SM_Real<ps>
484 , SIMCInstr<ps.PseudoInstr, SIEncodingFamily.SI>
490 let Inst{7-0} = !if(ps.has_offset, offset{7-0}, !if(ps.has_soffset, soffset, ?));
491 let Inst{8} = ps.has_offset;
492 let Inst{14-9} = !if(ps.has_sbase, sbase{6-1}, ?);
493 let Inst{21-15} = !if(ps.has_sdst, sdst{6-0}, ?);
499 defvar ps = NAME;
500 defvar immPs = !cast<SM_Load_Pseudo>(ps#_IMM);
505 defvar sgprPs = !cast<SM_Load_Pseudo>(ps#_SGPR);
528 class SMEM_Real_vi <bits<8> op, SM_Pseudo ps>
529 : SM_Real<ps>
530 , SIMCInstr<ps.PseudoInstr, SIEncodingFamily.VI>
536 let Inst{5-0} = !if(ps.has_sbase, sbase{6-1}, ?);
537 let Inst{12-6} = !if(ps.has_sdst, sdst{6-0}, ?);
544 !if(ps.has_offset, ps.has_soffset, !if(ps.has_soffset, 0, ?)),
548 let Inst{16} = !if(ps.has_glc, cpol{CPolBit.GLC}, ?);
553 let Inst{17} = ps.has_offset;
562 let Offset{6-0} = !if(ps.has_offset, offset{6-0},
563 !if(ps.has_soffset, soffset{6-0}, ?));
564 let Offset{20-7} = !if(ps.has_offset, offset{20-7}, ?);
568 let Inst{63-57} = !if(!and(IsGFX9SpecificEncoding, ps.has_soffset),
572 class SMEM_Real_Load_vi<bits<8> op, string ps>
573 : SMEM_Real_vi<op, !cast<SM_Pseudo>(ps)>;
587 defvar ps = NAME;
588 def _IMM_vi : SMEM_Real_Load_vi <op, ps#"_IMM">;
589 def _SGPR_vi : SMEM_Real_Load_vi <op, ps#"_SGPR">;
590 def _SGPR_alt_gfx9 : SMEM_Real_Load_vi <op, ps#"_SGPR">,
593 def _SGPR_IMM_gfx9 : SMEM_Real_Load_vi <op, ps#"_SGPR_IMM">;
596 class SMEM_Real_Store_Base_vi <bits<8> op, SM_Pseudo ps> : SMEM_Real_vi <op, ps> {
601 let Inst{12-6} = !if(ps.has_sdst, sdata{6-0}, ?);
604 class SMEM_Real_Store_vi <bits<8> op, string ps>
605 : SMEM_Real_Store_Base_vi <op, !cast<SM_Pseudo>(ps)>;
608 defvar ps = NAME;
609 def _IMM_vi : SMEM_Real_Store_vi <op, ps#"_IMM">;
610 def _SGPR_vi : SMEM_Real_Store_vi <op, ps#"_SGPR">;
611 def _SGPR_alt_gfx9 : SMEM_Real_Store_vi <op, ps#"_SGPR">,
614 def _SGPR_IMM_gfx9 : SMEM_Real_Store_vi <op, ps#"_SGPR_IMM">;
618 defvar ps = NAME;
619 def _IMM_vi : SMEM_Real_Store_Base_vi <op, !cast<SM_Probe_Pseudo>(ps#_IMM)>;
620 def _SGPR_vi : SMEM_Real_Store_Base_vi <op, !cast<SM_Probe_Pseudo>(ps#_SGPR)>;
622 : SMEM_Real_Store_Base_vi <op, !cast<SM_Probe_Pseudo>(ps#_SGPR)>,
626 : SMEM_Real_Store_Base_vi <op, !cast<SM_Probe_Pseudo>(ps#_SGPR_IMM)>;
671 class SMEM_Atomic_Real_vi <bits<8> op, SM_Atomic_Pseudo ps>
672 : SMEM_Real_vi <op, ps> {
676 let Constraints = ps.Constraints;
677 let DisableEncoding = ps.DisableEncoding;
679 let cpol{CPolBit.GLC} = ps.glc;
680 let Inst{12-6} = !if(ps.glc, sdst{6-0}, sdata{6-0});
684 defvar ps = NAME;
685 def _IMM_vi : SMEM_Atomic_Real_vi <op, !cast<SM_Atomic_Pseudo>(ps#_IMM)>;
686 def _SGPR_vi : SMEM_Atomic_Real_vi <op, !cast<SM_Atomic_Pseudo>(ps#_SGPR)>;
688 : SMEM_Atomic_Real_vi <op, !cast<SM_Atomic_Pseudo>(ps#_SGPR)>,
692 : SMEM_Atomic_Real_vi <op, !cast<SM_Atomic_Pseudo>(ps#_SGPR_IMM)>;
693 def _IMM_RTN_vi : SMEM_Atomic_Real_vi <op, !cast<SM_Atomic_Pseudo>(ps#_IMM_RTN)>;
694 def _SGPR_RTN_vi : SMEM_Atomic_Real_vi <op, !cast<SM_Atomic_Pseudo>(ps#_SGPR_RTN)>;
696 : SMEM_Atomic_Real_vi <op, !cast<SM_Atomic_Pseudo>(ps#_SGPR_RTN)>,
700 : SMEM_Atomic_Real_vi <op, !cast<SM_Atomic_Pseudo>(ps#_SGPR_IMM_RTN)>;
760 defvar ps = NAME;
761 def _IMM_vi : SMEM_Real_vi <op, !cast<SM_Discard_Pseudo>(ps#_IMM)>;
762 def _SGPR_vi : SMEM_Real_vi <op, !cast<SM_Discard_Pseudo>(ps#_SGPR)>;
763 def _SGPR_alt_gfx9 : SMEM_Real_vi <op, !cast<SM_Discard_Pseudo>(ps#_SGPR)>,
766 def _SGPR_IMM_gfx9 : SMEM_Real_vi <op, !cast<SM_Discard_Pseudo>(ps#_SGPR_IMM)>;
778 class SMRD_Real_Load_IMM_ci <bits<5> op, SM_Load_Pseudo ps> :
779 SM_Real<ps>,
784 let InOperandList = (ins ps.BaseClass:$sbase, smrd_literal_offset:$offset, CPol:$cpol);
806 class SMRD_Real_ci <bits<5> op, SM_Pseudo ps>
807 : SM_Real<ps>
808 , SIMCInstr<ps.PseudoInstr, SIEncodingFamily.SI>
814 let Inst{7-0} = !if(ps.has_offset, offset{7-0}, !if(ps.has_soffset, soffset, ?));
815 let Inst{8} = ps.has_offset;
816 let Inst{14-9} = !if(ps.has_sbase, sbase{6-1}, ?);
817 let Inst{21-15} = !if(ps.has_sdst, sdst{6-0}, ?);
1155 class SMEM_Real_10Plus_common<bits<8> op, SM_Pseudo ps, string opName,
1157 SM_Real<ps, opName>, SIMCInstr<ps.PseudoInstr, subtarget>, Enc64 {
1158 let Inst{5-0} = !if(ps.has_sbase, sbase{6-1}, ?);
1159 let Inst{12-6} = !if(ps.has_sdst, sdst{6-0}, ?);
1164 let Inst{52-32} = !if(ps.has_offset, offset{20-0}, !if(ps.has_soffset, 0, ?));
1165 let Inst{63-57} = !if(ps.has_soffset, soffset{6-0},
1166 !if(ps.has_offset, sgpr_null.HWEncoding{6-0}, ?));
1169 class SMEM_Real_gfx10<bits<8> op, SM_Pseudo ps>
1170 : SMEM_Real_10Plus_common<op, ps, ps.Mnemonic, SIEncodingFamily.GFX10,
1174 let Inst{14} = !if(ps.has_dlc, cpol{CPolBit.DLC}, ?);
1175 let Inst{16} = !if(ps.has_glc, cpol{CPolBit.GLC}, ?);
1178 class SMEM_Real_Load_gfx10<bits<8> op, string ps>
1179 : SMEM_Real_gfx10<op, !cast<SM_Pseudo>(ps)>;
1182 defvar ps = NAME;
1183 def _IMM_gfx10 : SMEM_Real_Load_gfx10<op, ps#"_IMM">;
1184 def _SGPR_gfx10 : SMEM_Real_Load_gfx10<op, ps#"_SGPR">;
1185 def _SGPR_IMM_gfx10 : SMEM_Real_Load_gfx10<op, ps#"_SGPR_IMM">;
1188 class SMEM_Real_Store_gfx10<bits<8> op, SM_Pseudo ps> : SMEM_Real_gfx10<op, ps> {
1192 let Inst{12-6} = !if(ps.has_sdst, sdata{6-0}, ?);
1196 defvar ps = NAME;
1197 defvar immPs = !cast<SM_Store_Pseudo>(ps#_IMM);
1200 defvar sgprPs = !cast<SM_Store_Pseudo>(ps#_SGPR);
1203 defvar sgprImmPs = !cast<SM_Store_Pseudo>(ps#_SGPR_IMM);
1242 defvar ps = NAME;
1243 def _IMM_gfx10 : SMEM_Real_Store_gfx10 <op, !cast<SM_Pseudo>(ps#_IMM)>;
1244 def _SGPR_gfx10 : SMEM_Real_Store_gfx10 <op, !cast<SM_Pseudo>(ps#_SGPR)>;
1246 : SMEM_Real_Store_gfx10 <op, !cast<SM_Pseudo>(ps#_SGPR_IMM)>;
1252 class SMEM_Atomic_Real_gfx10 <bits<8> op, SM_Atomic_Pseudo ps>
1253 : SMEM_Real_gfx10 <op, ps> {
1257 let Constraints = ps.Constraints;
1258 let DisableEncoding = ps.DisableEncoding;
1260 let cpol{CPolBit.GLC} = ps.glc;
1262 let Inst{14} = !if(ps.has_dlc, cpol{CPolBit.DLC}, 0);
1263 let Inst{12-6} = !if(ps.glc, sdst{6-0}, sdata{6-0});
1267 defvar ps = NAME;
1268 def _IMM_gfx10 : SMEM_Atomic_Real_gfx10 <op, !cast<SM_Atomic_Pseudo>(ps#_IMM)>;
1269 def _SGPR_gfx10 : SMEM_Atomic_Real_gfx10 <op, !cast<SM_Atomic_Pseudo>(ps#_SGPR)>;
1270 def _SGPR_IMM_gfx10 : SMEM_Atomic_Real_gfx10 <op, !cast<SM_Atomic_Pseudo>(ps#_SGPR_IMM)>;
1271 def _IMM_RTN_gfx10 : SMEM_Atomic_Real_gfx10 <op, !cast<SM_Atomic_Pseudo>(ps#_IMM_RTN)>;
1272 def _SGPR_RTN_gfx10 : SMEM_Atomic_Real_gfx10 <op, !cast<SM_Atomic_Pseudo>(ps#_SGPR_RTN)>;
1273 def _SGPR_IMM_RTN_gfx10 : SMEM_Atomic_Real_gfx10 <op, !cast<SM_Atomic_Pseudo>(ps#_SGPR_IMM_RTN)>;
1333 defvar ps = NAME;
1334 def _IMM_gfx10 : SMEM_Real_gfx10 <op, !cast<SM_Pseudo>(ps#_IMM)>;
1335 def _SGPR_gfx10 : SMEM_Real_gfx10 <op, !cast<SM_Pseudo>(ps#_SGPR)>;
1336 def _SGPR_IMM_gfx10 : SMEM_Real_gfx10 <op, !cast<SM_Pseudo>(ps#_SGPR_IMM)>;
1355 class SMEM_Real_gfx11<bits<8> op, SM_Pseudo ps, string opName = ps.Mnemonic> :
1356 SMEM_Real_10Plus_common<op, ps, opName, SIEncodingFamily.GFX11,
1360 let Inst{13} = !if(ps.has_dlc, cpol{CPolBit.DLC}, 0);
1361 let Inst{14} = !if(ps.has_glc, cpol{CPolBit.GLC}, 0);
1364 class SMEM_Real_Load_gfx11<bits<8> op, string ps, string opName> :
1365 SMEM_Real_gfx11<op, !cast<SM_Pseudo>(ps), opName>;
1367 multiclass SM_Real_Loads_gfx11<bits<8> op, string ps> {
1369 def _IMM_gfx11 : SMEM_Real_Load_gfx11<op, ps#"_IMM", opName>;
1370 def _SGPR_gfx11 : SMEM_Real_Load_gfx11<op, ps#"_SGPR", opName>;
1371 def _SGPR_IMM_gfx11 : SMEM_Real_Load_gfx11<op, ps#"_SGPR_IMM", opName>;
1372 def : AMDGPUMnemonicAlias<!cast<SM_Pseudo>(ps#"_IMM").Mnemonic, opName> {
1392 class SMEM_Real_Store_gfx11 <bits<8> op, SM_Pseudo ps> : SMEM_Real_gfx11<op, ps> {
1397 let Inst{12-6} = !if(ps.has_sdst, sdata{6-0}, ?);
1401 defvar ps = NAME;
1402 def _IMM_gfx11 : SMEM_Real_Store_gfx11 <op, !cast<SM_Probe_Pseudo>(ps#_IMM)>;
1403 def _SGPR_gfx11 : SMEM_Real_Store_gfx11 <op, !cast<SM_Probe_Pseudo>(ps#_SGPR)>;
1405 : SMEM_Real_Store_gfx11 <op, !cast<SM_Probe_Pseudo>(ps#_SGPR_IMM)>;
1415 class SMEM_Real_gfx12Plus<bits<6> op, SM_Pseudo ps, string opName,
1417 SM_Real<ps, opName>, SIMCInstr<ps.PseudoInstr, subtarget>, Enc64 {
1422 let Inst{55-32} = !if(ps.has_offset, offset{23-0}, !if(ps.has_soffset, 0, ?));
1423 let Inst{63-57} = !if(ps.has_soffset, soffset{6-0},
1424 !if(ps.has_offset, sgpr_null.HWEncoding{6-0}, ?));
1427 class SMEM_Real_gfx12<bits<6> op, SM_Pseudo ps, string opName = ps.Mnemonic> :
1428 SMEM_Real_gfx12Plus<op, ps, opName, SIEncodingFamily.GFX12,
1433 let Inst{5-0} = !if(ps.has_sbase, sbase{6-1}, ?);
1434 let Inst{12-6} = !if(ps.has_sdst, sdst{6-0}, ?);
1437 class SMEM_Real_Prefetch_gfx12<bits<6> op, SM_Pseudo ps> :
1438 SMEM_Real_gfx12<op, ps> {
1443 let Inst{10-6} = !if(ps.has_sdst, sdata{4-0}, ?);
1446 class SMEM_Real_Load_gfx12<bits<6> op, string ps, string opName, OffsetMode offsets> :
1447 SMEM_Real_gfx12<op, !cast<SM_Pseudo>(ps # offsets.Variant), opName> {
1448 RegisterClass BaseClass = !cast<SM_Load_Pseudo>(ps # offsets.Variant).BaseClass;
1455 multiclass SM_Real_Loads_gfx12<bits<6> op, string ps = NAME> {
1457 def _IMM_gfx12 : SMEM_Real_Load_gfx12<op, ps, opName, IMM_Offset>;
1458 def _SGPR_IMM_gfx12 : SMEM_Real_Load_gfx12<op, ps, opName, SGPR_IMM_OptOffset>;
1494 defvar ps = NAME;
1495 def _IMM_gfx12 : SMEM_Real_Prefetch_gfx12<op, !cast<SM_Probe_Pseudo>(ps#_IMM)>;
1496 def _SGPR_IMM_gfx12 : SMEM_Real_Prefetch_gfx12<op, !cast<SM_Probe_Pseudo>(ps#_SGPR_OPT_IMM)>;