Lines Matching full:src0
93 int Src0Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::src0); in foldImmediates()
95 // Try to fold Src0 in foldImmediates()
96 MachineOperand &Src0 = MI.getOperand(Src0Idx); in foldImmediates() local
97 if (Src0.isReg()) { in foldImmediates()
98 Register Reg = Src0.getReg(); in foldImmediates()
107 Src0.ChangeToImmediate(MovSrc.getImm()); in foldImmediates()
110 Src0.ChangeToFrameIndex(MovSrc.getIndex()); in foldImmediates()
113 Src0.ChangeToGA(MovSrc.getGlobal(), MovSrc.getOffset(), in foldImmediates()
129 // We have failed to fold src0, so commute the instruction and try again. in foldImmediates()
242 // cmpk requires src0 to be a register in shrinkScalarCompare()
243 const MachineOperand &Src0 = MI.getOperand(0); in shrinkScalarCompare() local
244 if (!Src0.isReg()) in shrinkScalarCompare()
418 MachineOperand &Src0 = *TII->getNamedOperand(MI, AMDGPU::OpName::src0); in shrinkMadFma() local
429 else if (Src0.isReg() && TRI->isVGPR(*MRI, Src0.getReg())) in shrinkMadFma()
458 else if (Src0.isImm() && !TII->isInlineConstant(Src0)) in shrinkMadFma()
490 // Swap Src0 and Src1 by building a new instruction. in shrinkMadFma()
494 .add(Src0) in shrinkMadFma()
512 MachineOperand *Src0 = &MI.getOperand(1); in shrinkScalarLogicOp() local
514 MachineOperand *SrcReg = Src0; in shrinkScalarLogicOp()
562 Src0->ChangeToImmediate(NewImm); in shrinkScalarLogicOp()
847 MachineOperand *Src0 = &MI.getOperand(1); in runOnMachineFunction() local
850 if (!Src0->isReg() && Src1->isReg()) { in runOnMachineFunction()
852 std::swap(Src0, Src1); in runOnMachineFunction()
858 if (Dest->getReg().isVirtual() && Src0->isReg()) { in runOnMachineFunction()
859 MRI->setRegAllocationHint(Dest->getReg(), 0, Src0->getReg()); in runOnMachineFunction()
860 MRI->setRegAllocationHint(Src0->getReg(), 0, Dest->getReg()); in runOnMachineFunction()
864 if (Src0->isReg() && Src0->getReg() == Dest->getReg()) { in runOnMachineFunction()