Lines Matching refs:SB
1727 void SIRegisterInfo::buildVGPRSpillLoadStore(SGPRSpillBuilder &SB, int Index, in buildVGPRSpillLoadStore() argument
1731 MachineFrameInfo &FrameInfo = SB.MF.getFrameInfo(); in buildVGPRSpillLoadStore()
1735 FrameInfo.isFixedObjectIndex(Index) && hasBasePointer(SB.MF) in buildVGPRSpillLoadStore()
1737 : getFrameRegister(SB.MF); in buildVGPRSpillLoadStore()
1740 MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(SB.MF, Index); in buildVGPRSpillLoadStore()
1741 MachineMemOperand *MMO = SB.MF.getMachineMemOperand( in buildVGPRSpillLoadStore()
1743 SB.EltSize, Alignment); in buildVGPRSpillLoadStore()
1748 buildSpillLoadStore(*SB.MBB, SB.MI, SB.DL, Opc, Index, SB.TmpVGPR, false, in buildVGPRSpillLoadStore()
1749 FrameReg, (int64_t)Offset * SB.EltSize, MMO, SB.RS); in buildVGPRSpillLoadStore()
1753 buildSpillLoadStore(*SB.MBB, SB.MI, SB.DL, Opc, Index, SB.TmpVGPR, IsKill, in buildVGPRSpillLoadStore()
1754 FrameReg, (int64_t)Offset * SB.EltSize, MMO, SB.RS); in buildVGPRSpillLoadStore()
1756 SB.MFI.addToSpilledVGPRs(1); in buildVGPRSpillLoadStore()
1764 SGPRSpillBuilder SB(*this, *ST.getInstrInfo(), isWave32, MI, Index, RS); in spillSGPR() local
1767 SpillToPhysVGPRLane ? SB.MFI.getSGPRSpillToPhysicalVGPRLanes(Index) in spillSGPR()
1768 : SB.MFI.getSGPRSpillToVirtualVGPRLanes(Index); in spillSGPR()
1773 assert(SpillToVGPR || (SB.SuperReg != SB.MFI.getStackPtrOffsetReg() && in spillSGPR()
1774 SB.SuperReg != SB.MFI.getFrameOffsetReg())); in spillSGPR()
1778 assert(SB.NumSubRegs == VGPRSpills.size() && in spillSGPR()
1781 for (unsigned i = 0, e = SB.NumSubRegs; i < e; ++i) { in spillSGPR()
1783 SB.NumSubRegs == 1 in spillSGPR()
1784 ? SB.SuperReg in spillSGPR()
1785 : Register(getSubReg(SB.SuperReg, SB.SplitParts[i])); in spillSGPR()
1789 bool IsLastSubreg = i == SB.NumSubRegs - 1; in spillSGPR()
1790 bool UseKill = SB.IsKill && IsLastSubreg; in spillSGPR()
1795 auto MIB = BuildMI(*SB.MBB, MI, SB.DL, in spillSGPR()
1796 SB.TII.get(AMDGPU::SI_SPILL_S32_TO_VGPR), Spill.VGPR) in spillSGPR()
1807 if (IsFirstSubreg && SB.NumSubRegs > 1) { in spillSGPR()
1810 MIB.addReg(SB.SuperReg, RegState::ImplicitDefine); in spillSGPR()
1813 if (SB.NumSubRegs > 1 && (IsFirstSubreg || IsLastSubreg)) in spillSGPR()
1814 MIB.addReg(SB.SuperReg, getKillRegState(UseKill) | RegState::Implicit); in spillSGPR()
1821 SB.prepare(); in spillSGPR()
1824 unsigned SubKillState = getKillRegState((SB.NumSubRegs == 1) && SB.IsKill); in spillSGPR()
1827 auto PVD = SB.getPerVGPRData(); in spillSGPR()
1834 e = std::min((Offset + 1) * PVD.PerVGPR, SB.NumSubRegs); in spillSGPR()
1837 SB.NumSubRegs == 1 in spillSGPR()
1838 ? SB.SuperReg in spillSGPR()
1839 : Register(getSubReg(SB.SuperReg, SB.SplitParts[i])); in spillSGPR()
1842 BuildMI(*SB.MBB, MI, SB.DL, in spillSGPR()
1843 SB.TII.get(AMDGPU::SI_SPILL_S32_TO_VGPR), SB.TmpVGPR) in spillSGPR()
1846 .addReg(SB.TmpVGPR, TmpVGPRFlags); in spillSGPR()
1858 if (SB.NumSubRegs > 1) { in spillSGPR()
1861 if (i + 1 == SB.NumSubRegs) in spillSGPR()
1862 SuperKillState |= getKillRegState(SB.IsKill); in spillSGPR()
1863 WriteLane.addReg(SB.SuperReg, RegState::Implicit | SuperKillState); in spillSGPR()
1868 SB.readWriteTmpVGPR(Offset, /*IsLoad*/ false); in spillSGPR()
1871 SB.restore(); in spillSGPR()
1875 SB.MFI.addToSpilledSGPRs(SB.NumSubRegs); in spillSGPR()
1878 LIS->removeAllRegUnitsForPhysReg(SB.SuperReg); in spillSGPR()
1887 SGPRSpillBuilder SB(*this, *ST.getInstrInfo(), isWave32, MI, Index, RS); in restoreSGPR() local
1890 SpillToPhysVGPRLane ? SB.MFI.getSGPRSpillToPhysicalVGPRLanes(Index) in restoreSGPR()
1891 : SB.MFI.getSGPRSpillToVirtualVGPRLanes(Index); in restoreSGPR()
1897 for (unsigned i = 0, e = SB.NumSubRegs; i < e; ++i) { in restoreSGPR()
1899 SB.NumSubRegs == 1 in restoreSGPR()
1900 ? SB.SuperReg in restoreSGPR()
1901 : Register(getSubReg(SB.SuperReg, SB.SplitParts[i])); in restoreSGPR()
1904 auto MIB = BuildMI(*SB.MBB, MI, SB.DL, in restoreSGPR()
1905 SB.TII.get(AMDGPU::SI_RESTORE_S32_FROM_VGPR), SubReg) in restoreSGPR()
1908 if (SB.NumSubRegs > 1 && i == 0) in restoreSGPR()
1909 MIB.addReg(SB.SuperReg, RegState::ImplicitDefine); in restoreSGPR()
1918 SB.prepare(); in restoreSGPR()
1921 auto PVD = SB.getPerVGPRData(); in restoreSGPR()
1925 SB.readWriteTmpVGPR(Offset, /*IsLoad*/ true); in restoreSGPR()
1929 e = std::min((Offset + 1) * PVD.PerVGPR, SB.NumSubRegs); in restoreSGPR()
1932 SB.NumSubRegs == 1 in restoreSGPR()
1933 ? SB.SuperReg in restoreSGPR()
1934 : Register(getSubReg(SB.SuperReg, SB.SplitParts[i])); in restoreSGPR()
1937 auto MIB = BuildMI(*SB.MBB, MI, SB.DL, in restoreSGPR()
1938 SB.TII.get(AMDGPU::SI_RESTORE_S32_FROM_VGPR), SubReg) in restoreSGPR()
1939 .addReg(SB.TmpVGPR, getKillRegState(LastSubReg)) in restoreSGPR()
1941 if (SB.NumSubRegs > 1 && i == 0) in restoreSGPR()
1942 MIB.addReg(SB.SuperReg, RegState::ImplicitDefine); in restoreSGPR()
1952 SB.restore(); in restoreSGPR()
1958 LIS->removeAllRegUnitsForPhysReg(SB.SuperReg); in restoreSGPR()
1966 SGPRSpillBuilder SB(*this, *ST.getInstrInfo(), isWave32, MI, SGPR, false, 0, in spillEmergencySGPR() local
1968 SB.prepare(); in spillEmergencySGPR()
1970 unsigned SubKillState = getKillRegState((SB.NumSubRegs == 1) && SB.IsKill); in spillEmergencySGPR()
1971 auto PVD = SB.getPerVGPRData(); in spillEmergencySGPR()
1976 e = std::min((Offset + 1) * PVD.PerVGPR, SB.NumSubRegs); in spillEmergencySGPR()
1979 SB.NumSubRegs == 1 in spillEmergencySGPR()
1980 ? SB.SuperReg in spillEmergencySGPR()
1981 : Register(getSubReg(SB.SuperReg, SB.SplitParts[i])); in spillEmergencySGPR()
1984 BuildMI(*SB.MBB, MI, SB.DL, SB.TII.get(AMDGPU::V_WRITELANE_B32), in spillEmergencySGPR()
1985 SB.TmpVGPR) in spillEmergencySGPR()
1988 .addReg(SB.TmpVGPR, TmpVGPRFlags); in spillEmergencySGPR()
1992 if (SB.NumSubRegs > 1) { in spillEmergencySGPR()
1995 if (i + 1 == SB.NumSubRegs) in spillEmergencySGPR()
1996 SuperKillState |= getKillRegState(SB.IsKill); in spillEmergencySGPR()
1997 WriteLane.addReg(SB.SuperReg, RegState::Implicit | SuperKillState); in spillEmergencySGPR()
2005 SB.setMI(&RestoreMBB, MI); in spillEmergencySGPR()
2011 e = std::min((Offset + 1) * PVD.PerVGPR, SB.NumSubRegs); in spillEmergencySGPR()
2014 SB.NumSubRegs == 1 in spillEmergencySGPR()
2015 ? SB.SuperReg in spillEmergencySGPR()
2016 : Register(getSubReg(SB.SuperReg, SB.SplitParts[i])); in spillEmergencySGPR()
2018 auto MIB = BuildMI(*SB.MBB, MI, SB.DL, SB.TII.get(AMDGPU::V_READLANE_B32), in spillEmergencySGPR()
2020 .addReg(SB.TmpVGPR, getKillRegState(LastSubReg)) in spillEmergencySGPR()
2022 if (SB.NumSubRegs > 1 && i == 0) in spillEmergencySGPR()
2023 MIB.addReg(SB.SuperReg, RegState::ImplicitDefine); in spillEmergencySGPR()
2026 SB.restore(); in spillEmergencySGPR()
2028 SB.MFI.addToSpilledSGPRs(SB.NumSubRegs); in spillEmergencySGPR()