72 struct SGPRSpillBuilder {  struct
73   struct PerVGPRData {
80   Register SuperReg;
81   MachineBasicBlock::iterator MI;
82   ArrayRef<int16_t> SplitParts;
83   unsigned NumSubRegs;
84   bool IsKill;
85   const DebugLoc &DL;
90   Register TmpVGPR = AMDGPU::NoRegister;
92   int TmpVGPRIndex = 0;
94   bool TmpVGPRLive = false;
96   Register SavedExecReg = AMDGPU::NoRegister;
98   int Index;
99   unsigned EltSize = 4;
101   RegScavenger *RS;
102   MachineBasicBlock *MBB;
103   MachineFunction &MF;
104   SIMachineFunctionInfo &MFI;
105   const SIInstrInfo &TII;
106   const SIRegisterInfo &TRI;
107   bool IsWave32;
108   Register ExecReg;
109   unsigned MovOpc;
110   unsigned NotOpc;
112   SGPRSpillBuilder(const SIRegisterInfo &TRI, const SIInstrInfo &TII,  in SGPRSpillBuilder()  argument
118   SGPRSpillBuilder(const SIRegisterInfo &TRI, const SIInstrInfo &TII,  in SGPRSpillBuilder()  function
144   PerVGPRData getPerVGPRData() {  in getPerVGPRData()
165   void prepare() {  in prepare()
247   void restore() {  in restore()
288   void readWriteTmpVGPR(unsigned Offset, bool IsLoad) {  in readWriteTmpVGPR()
311   void setMI(MachineBasicBlock *NewMBB, MachineBasicBlock::iterator NewMI) {  in setMI()