92                          const MachineInstr &Sel, const MachineInstr &And) {  in isDefBetween()  argument
94   SlotIndex SelIdx = LIS->getInstructionIndex(Sel).getRegSlot();  in isDefBetween()
165   auto *Sel = TRI->findReachingDef(SelReg, Op1->getSubReg(), *Cmp, *MRI, LIS);  in optimizeVcndVcmpPair()  local
166   if (!Sel || Sel->getOpcode() != AMDGPU::V_CNDMASK_B32_e64)  in optimizeVcndVcmpPair()
169   if (TII->hasModifiersSet(*Sel, AMDGPU::OpName::src0_modifiers) ||  in optimizeVcndVcmpPair()
170       TII->hasModifiersSet(*Sel, AMDGPU::OpName::src1_modifiers))  in optimizeVcndVcmpPair()
173   Op1 = TII->getNamedOperand(*Sel, AMDGPU::OpName::src0);  in optimizeVcndVcmpPair()
174   Op2 = TII->getNamedOperand(*Sel, AMDGPU::OpName::src1);  in optimizeVcndVcmpPair()
175   MachineOperand *CC = TII->getNamedOperand(*Sel, AMDGPU::OpName::src2);  in optimizeVcndVcmpPair()
184   if (isDefBetween(*TRI, LIS, CCReg, *Sel, *And))  in optimizeVcndVcmpPair()
189   SlotIndex SelIdx = LIS->getInstructionIndex(*Sel);  in optimizeVcndVcmpPair()
198   LLVM_DEBUG(dbgs() << "Folding sequence:\n\t" << *Sel << '\t' << *Cmp << '\t'  in optimizeVcndVcmpPair()
251       LLVM_DEBUG(dbgs() << "Erasing: " << *Sel << '\n');  in optimizeVcndVcmpPair()
254       LIS->RemoveMachineInstrFromMaps(*Sel);  in optimizeVcndVcmpPair()
255       bool ShrinkSel = Sel->getOperand(0).readsReg();  in optimizeVcndVcmpPair()
256       Sel->eraseFromParent();  in optimizeVcndVcmpPair()