Lines Matching refs:AMDGPU
98 case AMDGPU::COPY: in isCopyFromExec()
99 case AMDGPU::S_MOV_B64: in isCopyFromExec()
100 case AMDGPU::S_MOV_B64_term: in isCopyFromExec()
101 case AMDGPU::S_MOV_B32: in isCopyFromExec()
102 case AMDGPU::S_MOV_B32_term: { in isCopyFromExec()
109 return AMDGPU::NoRegister; in isCopyFromExec()
115 case AMDGPU::COPY: in isCopyToExec()
116 case AMDGPU::S_MOV_B64: in isCopyToExec()
117 case AMDGPU::S_MOV_B32: { in isCopyToExec()
123 case AMDGPU::S_MOV_B64_term: in isCopyToExec()
124 case AMDGPU::S_MOV_B32_term: in isCopyToExec()
135 case AMDGPU::S_AND_B64: in isLogicalOpOnExec()
136 case AMDGPU::S_OR_B64: in isLogicalOpOnExec()
137 case AMDGPU::S_XOR_B64: in isLogicalOpOnExec()
138 case AMDGPU::S_ANDN2_B64: in isLogicalOpOnExec()
139 case AMDGPU::S_ORN2_B64: in isLogicalOpOnExec()
140 case AMDGPU::S_NAND_B64: in isLogicalOpOnExec()
141 case AMDGPU::S_NOR_B64: in isLogicalOpOnExec()
142 case AMDGPU::S_XNOR_B64: { in isLogicalOpOnExec()
144 if (Src1.isReg() && Src1.getReg() == AMDGPU::EXEC) in isLogicalOpOnExec()
147 if (Src2.isReg() && Src2.getReg() == AMDGPU::EXEC) in isLogicalOpOnExec()
151 case AMDGPU::S_AND_B32: in isLogicalOpOnExec()
152 case AMDGPU::S_OR_B32: in isLogicalOpOnExec()
153 case AMDGPU::S_XOR_B32: in isLogicalOpOnExec()
154 case AMDGPU::S_ANDN2_B32: in isLogicalOpOnExec()
155 case AMDGPU::S_ORN2_B32: in isLogicalOpOnExec()
156 case AMDGPU::S_NAND_B32: in isLogicalOpOnExec()
157 case AMDGPU::S_NOR_B32: in isLogicalOpOnExec()
158 case AMDGPU::S_XNOR_B32: { in isLogicalOpOnExec()
160 if (Src1.isReg() && Src1.getReg() == AMDGPU::EXEC_LO) in isLogicalOpOnExec()
163 if (Src2.isReg() && Src2.getReg() == AMDGPU::EXEC_LO) in isLogicalOpOnExec()
169 return AMDGPU::NoRegister; in isLogicalOpOnExec()
174 case AMDGPU::S_AND_B64: in getSaveExecOp()
175 return AMDGPU::S_AND_SAVEEXEC_B64; in getSaveExecOp()
176 case AMDGPU::S_OR_B64: in getSaveExecOp()
177 return AMDGPU::S_OR_SAVEEXEC_B64; in getSaveExecOp()
178 case AMDGPU::S_XOR_B64: in getSaveExecOp()
179 return AMDGPU::S_XOR_SAVEEXEC_B64; in getSaveExecOp()
180 case AMDGPU::S_ANDN2_B64: in getSaveExecOp()
181 return AMDGPU::S_ANDN2_SAVEEXEC_B64; in getSaveExecOp()
182 case AMDGPU::S_ORN2_B64: in getSaveExecOp()
183 return AMDGPU::S_ORN2_SAVEEXEC_B64; in getSaveExecOp()
184 case AMDGPU::S_NAND_B64: in getSaveExecOp()
185 return AMDGPU::S_NAND_SAVEEXEC_B64; in getSaveExecOp()
186 case AMDGPU::S_NOR_B64: in getSaveExecOp()
187 return AMDGPU::S_NOR_SAVEEXEC_B64; in getSaveExecOp()
188 case AMDGPU::S_XNOR_B64: in getSaveExecOp()
189 return AMDGPU::S_XNOR_SAVEEXEC_B64; in getSaveExecOp()
190 case AMDGPU::S_AND_B32: in getSaveExecOp()
191 return AMDGPU::S_AND_SAVEEXEC_B32; in getSaveExecOp()
192 case AMDGPU::S_OR_B32: in getSaveExecOp()
193 return AMDGPU::S_OR_SAVEEXEC_B32; in getSaveExecOp()
194 case AMDGPU::S_XOR_B32: in getSaveExecOp()
195 return AMDGPU::S_XOR_SAVEEXEC_B32; in getSaveExecOp()
196 case AMDGPU::S_ANDN2_B32: in getSaveExecOp()
197 return AMDGPU::S_ANDN2_SAVEEXEC_B32; in getSaveExecOp()
198 case AMDGPU::S_ORN2_B32: in getSaveExecOp()
199 return AMDGPU::S_ORN2_SAVEEXEC_B32; in getSaveExecOp()
200 case AMDGPU::S_NAND_B32: in getSaveExecOp()
201 return AMDGPU::S_NAND_SAVEEXEC_B32; in getSaveExecOp()
202 case AMDGPU::S_NOR_B32: in getSaveExecOp()
203 return AMDGPU::S_NOR_SAVEEXEC_B32; in getSaveExecOp()
204 case AMDGPU::S_XNOR_B32: in getSaveExecOp()
205 return AMDGPU::S_XNOR_SAVEEXEC_B32; in getSaveExecOp()
207 return AMDGPU::INSTRUCTION_LIST_END; in getSaveExecOp()
215 case AMDGPU::S_MOV_B32_term: { in removeTerminatorBit()
217 MI.setDesc(TII->get(RegSrc ? AMDGPU::COPY : AMDGPU::S_MOV_B32)); in removeTerminatorBit()
220 case AMDGPU::S_MOV_B64_term: { in removeTerminatorBit()
222 MI.setDesc(TII->get(RegSrc ? AMDGPU::COPY : AMDGPU::S_MOV_B64)); in removeTerminatorBit()
225 case AMDGPU::S_XOR_B64_term: { in removeTerminatorBit()
228 MI.setDesc(TII->get(AMDGPU::S_XOR_B64)); in removeTerminatorBit()
231 case AMDGPU::S_XOR_B32_term: { in removeTerminatorBit()
234 MI.setDesc(TII->get(AMDGPU::S_XOR_B32)); in removeTerminatorBit()
237 case AMDGPU::S_OR_B64_term: { in removeTerminatorBit()
240 MI.setDesc(TII->get(AMDGPU::S_OR_B64)); in removeTerminatorBit()
243 case AMDGPU::S_OR_B32_term: { in removeTerminatorBit()
246 MI.setDesc(TII->get(AMDGPU::S_OR_B32)); in removeTerminatorBit()
249 case AMDGPU::S_ANDN2_B64_term: { in removeTerminatorBit()
252 MI.setDesc(TII->get(AMDGPU::S_ANDN2_B64)); in removeTerminatorBit()
255 case AMDGPU::S_ANDN2_B32_term: { in removeTerminatorBit()
258 MI.setDesc(TII->get(AMDGPU::S_ANDN2_B32)); in removeTerminatorBit()
261 case AMDGPU::S_AND_B64_term: { in removeTerminatorBit()
264 MI.setDesc(TII->get(AMDGPU::S_AND_B64)); in removeTerminatorBit()
267 case AMDGPU::S_AND_B32_term: { in removeTerminatorBit()
270 MI.setDesc(TII->get(AMDGPU::S_AND_B32)); in removeTerminatorBit()
499 if (SaveExecOp == AMDGPU::INSTRUCTION_LIST_END) in optimizeExecSequence()
564 OtherInst->substituteRegister(CopyToExec, Exec, AMDGPU::NoSubRegister, in optimizeExecSequence()
578 const int NewOpcode = AMDGPU::getVCMPXOpFromVCMP(VCmp.getOpcode()); in optimizeVCMPSaveExecSequence()
583 MachineOperand *Src0 = TII->getNamedOperand(VCmp, AMDGPU::OpName::src0); in optimizeVCMPSaveExecSequence()
584 MachineOperand *Src1 = TII->getNamedOperand(VCmp, AMDGPU::OpName::src1); in optimizeVCMPSaveExecSequence()
591 unsigned MovOpcode = IsSGPR32 ? AMDGPU::S_MOV_B32 : AMDGPU::S_MOV_B64; in optimizeVCMPSaveExecSequence()
608 TryAddImmediateValueFromNamedOperand(AMDGPU::OpName::src0_modifiers); in optimizeVCMPSaveExecSequence()
611 TryAddImmediateValueFromNamedOperand(AMDGPU::OpName::src1_modifiers); in optimizeVCMPSaveExecSequence()
614 TryAddImmediateValueFromNamedOperand(AMDGPU::OpName::clamp); in optimizeVCMPSaveExecSequence()
644 ST->isWave32() ? AMDGPU::S_AND_SAVEEXEC_B32 : AMDGPU::S_AND_SAVEEXEC_B64; in tryRecordVCmpxAndSaveexecSequence()
653 MachineOperand *SaveExecSrc0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0); in tryRecordVCmpxAndSaveexecSequence()
669 return AMDGPU::getVCMPXOpFromVCMP(Check->getOpcode()) != -1 && in tryRecordVCmpxAndSaveexecSequence()
677 MachineOperand *VCmpDest = TII->getNamedOperand(*VCmp, AMDGPU::OpName::sdst); in tryRecordVCmpxAndSaveexecSequence()
681 MachineOperand *Src0 = TII->getNamedOperand(*VCmp, AMDGPU::OpName::src0); in tryRecordVCmpxAndSaveexecSequence()
686 MachineOperand *Src1 = TII->getNamedOperand(*VCmp, AMDGPU::OpName::src1); in tryRecordVCmpxAndSaveexecSequence()
731 ST->isWave32() ? AMDGPU::S_XOR_B32 : AMDGPU::S_XOR_B64; in tryRecordOrSaveexecXorSequence()
742 ? AMDGPU::S_OR_SAVEEXEC_B32 in tryRecordOrSaveexecXorSequence()
743 : AMDGPU::S_OR_SAVEEXEC_B64; in tryRecordOrSaveexecXorSequence()
769 const unsigned Andn2Opcode = ST->isWave32() ? AMDGPU::S_ANDN2_SAVEEXEC_B32 in optimizeOrSaveexecXorSequences()
770 : AMDGPU::S_ANDN2_SAVEEXEC_B64; in optimizeOrSaveexecXorSequences()