46   LOAD = 1u << 0,  enumerator
1058   assert(Op == SIMemOp::LOAD || Op == SIMemOp::STORE);  in enableVolatileAndOrNonTemporal()
1066     if (Op == SIMemOp::LOAD)  in enableVolatileAndOrNonTemporal()
1239   return insertWait(MI, Scope, AddrSpace, SIMemOp::LOAD | SIMemOp::STORE,  in insertRelease()
1411   assert(Op == SIMemOp::LOAD || Op == SIMemOp::STORE);  in enableVolatileAndOrNonTemporal()
1419     if (Op == SIMemOp::LOAD)  in enableVolatileAndOrNonTemporal()
1713   assert(Op == SIMemOp::LOAD || Op == SIMemOp::STORE);  in enableVolatileAndOrNonTemporal()
1884   Changed |= insertWait(MI, Scope, AddrSpace, SIMemOp::LOAD | SIMemOp::STORE,  in insertRelease()
1946   assert(Op == SIMemOp::LOAD || Op == SIMemOp::STORE);  in enableVolatileAndOrNonTemporal()
1954     if (Op == SIMemOp::LOAD) {  in enableVolatileAndOrNonTemporal()
2007       if ((Op & SIMemOp::LOAD) != SIMemOp::NONE)  in insertWait()
2019         if ((Op & SIMemOp::LOAD) != SIMemOp::NONE)  in insertWait()
2217   assert(Op == SIMemOp::LOAD || Op == SIMemOp::STORE);  in enableVolatileAndOrNonTemporal()
2225     if (Op == SIMemOp::LOAD)  in enableVolatileAndOrNonTemporal()
2326       if ((Op & SIMemOp::LOAD) != SIMemOp::NONE)  in insertWait()
2338         if ((Op & SIMemOp::LOAD) != SIMemOp::NONE)  in insertWait()
2516   insertWait(MI, Scope, AddrSpace, SIMemOp::LOAD | SIMemOp::STORE,  in insertRelease()
2533   assert(Op == SIMemOp::LOAD || Op == SIMemOp::STORE);  in enableVolatileAndOrNonTemporal()
2638                                 SIMemOp::LOAD | SIMemOp::STORE,  in expandLoad()
2646                                 SIMemOp::LOAD,  in expandLoad()
2661       MI, MOI.getInstrAddrSpace(), SIMemOp::LOAD, MOI.isVolatile(),  in expandLoad()
2720           MI, MOI.getScope(), OrderingAddrSpace, SIMemOp::LOAD | SIMemOp::STORE,  in expandAtomicFence()
2786                                 isAtomicRet(*MI) ? SIMemOp::LOAD :  in expandAtomicCmpxchgOrRmw()