Lines Matching full:bypassed
1009 /// to be bypassed as all memory operations by the same thread are in enableLoadCacheBypass()
1025 /// The L1 cache is write through so does not need to be bypassed. There is no in enableStoreCacheBypass()
1039 /// bypassed, and the GLC bit is instead used to indicate if they are in enableRMWCacheBypass()
1313 // on the same CU, and so the L1 does not need to be bypassed. in enableLoadCacheBypass()
1327 /// to be bypassed as all memory operations by the same thread are in enableLoadCacheBypass()
1362 /// to be bypassed as all memory operations by the same thread are in enableStoreCacheBypass()
1609 // on the same CU, and so the L1 does not need to be bypassed. Setting SC in enableLoadCacheBypass()
1623 /// to be bypassed as all memory operations by the same thread are in enableLoadCacheBypass()
1663 /// to be bypassed as all memory operations by the same thread are in enableStoreCacheBypass()
1910 // does not need to be bypassed. in enableLoadCacheBypass()
1924 /// to be bypassed as all memory operations by the same thread are in enableLoadCacheBypass()
2181 // does not need to be bypassed. in enableLoadCacheBypass()
2195 /// to be bypassed as all memory operations by the same thread are in enableLoadCacheBypass()
2601 // to be bypassed as all memory operations by the same thread are in setAtomicScope()