35 insertUndefLaneMask(MachineBasicBlock *MBB, MachineRegisterInfo *MRI,
76                      MachineBasicBlock *MBB) override;
77   void buildMergeLaneMasks(MachineBasicBlock &MBB,
144   bool isSource(MachineBasicBlock &MBB) const {  in isSource()
145     return ReachableMap.find(&MBB)->second;  in isSource()
162       MachineBasicBlock *MBB = Incoming.Block;  in analyze()  local
163       if (MBB == &DefBlock) {  in analyze()
168       ReachableMap.try_emplace(MBB, false);  in analyze()
169       ReachableOrdered.push_back(MBB);  in analyze()
173       if (TII->hasDivergentBranch(MBB) && PDT.dominates(&DefBlock, MBB))  in analyze()
174         append_range(Stack, MBB->successors());  in analyze()
178       MachineBasicBlock *MBB = Stack.pop_back_val();  in analyze()  local
179       if (!ReachableMap.try_emplace(MBB, false).second)  in analyze()
181       ReachableOrdered.push_back(MBB);  in analyze()
183       append_range(Stack, MBB->successors());  in analyze()
186     for (MachineBasicBlock *MBB : ReachableOrdered) {  in analyze()
188       for (MachineBasicBlock *Pred : MBB->predecessors()) {  in analyze()
196         ReachableMap[MBB] = true;  in analyze()
269   void initialize(MachineBasicBlock &MBB) {  in initialize()  argument
277     DefBlock = &MBB;  in initialize()
331   bool inLoopLevel(MachineBasicBlock &MBB, unsigned LoopLevel,  in inLoopLevel()  argument
333     auto DomIt = Visited.find(&MBB);  in inLoopLevel()
338       if (Incoming.Block == &MBB)  in inLoopLevel()
369       MachineBasicBlock *MBB = Stack.pop_back_val();  in advanceLevel()  local
370       if (!PDT.dominates(VisitedPostDom, MBB))  in advanceLevel()
371         NextLevel.push_back(MBB);  in advanceLevel()
373       Visited[MBB] = Level;  in advanceLevel()
374       VisitedDom = DT.findNearestCommonDominator(VisitedDom, MBB);  in advanceLevel()
376       for (MachineBasicBlock *Succ : MBB->successors()) {  in advanceLevel()
378           if (MBB == VisitedPostDom)  in advanceLevel()
386           if (MBB == VisitedPostDom)  in advanceLevel()
422 insertUndefLaneMask(MachineBasicBlock *MBB, MachineRegisterInfo *MRI,  in insertUndefLaneMask()  argument
424   MachineFunction &MF = *MBB->getParent();  in insertUndefLaneMask()
428   BuildMI(*MBB, MBB->getFirstTerminator(), {}, TII->get(AMDGPU::IMPLICIT_DEF),  in insertUndefLaneMask()
472   for (MachineBasicBlock &MBB : *MF) {  in lowerCopiesFromI1()
473     for (MachineInstr &MI : MBB) {  in lowerCopiesFromI1()
495       BuildMI(MBB, MI, DL, TII->get(AMDGPU::V_CNDMASK_B32_e64), DstReg)  in lowerCopiesFromI1()
554     MachineBasicBlock &MBB = *MI->getParent();  in lowerPhis()  local
555     if (&MBB != PrevMBB) {  in lowerPhis()
556       LF.initialize(MBB);  in lowerPhis()
557       PrevMBB = &MBB;  in lowerPhis()
583     std::vector<MachineBasicBlock *> DomBlocks = {&MBB};  in lowerPhis()
616       PIA.analyze(MBB, Incomings);  in lowerPhis()
618       for (MachineBasicBlock *MBB : PIA.predecessors())  in lowerPhis()
620             MBB, insertUndefLaneMask(MBB, MRI, LaneMaskRegAttrs));  in lowerPhis()
644     Register NewReg = SSAUpdater.GetValueInMiddleOfBlock(&MBB);  in lowerPhis()
646       replaceDstReg(NewReg, DstReg, &MBB);  in lowerPhis()
661   for (MachineBasicBlock &MBB : *MF) {  in lowerCopiesToI1()
662     LF.initialize(MBB);  in lowerCopiesToI1()
664     for (MachineInstr &MI : MBB) {  in lowerCopiesToI1()
695         BuildMI(MBB, MI, DL, TII->get(AMDGPU::V_CMP_NE_U32_e64), TmpReg)  in lowerCopiesToI1()
707       std::vector<MachineBasicBlock *> DomBlocks = {&MBB};  in lowerCopiesToI1()
716         SSAUpdater.AddAvailableValue(&MBB, DstReg);  in lowerCopiesToI1()
719         buildMergeLaneMasks(MBB, MI, DL, DstReg,  in lowerCopiesToI1()
720                             SSAUpdater.GetValueInMiddleOfBlock(&MBB), SrcReg);  in lowerCopiesToI1()
785 PhiLoweringHelper::getSaluInsertionAtEnd(MachineBasicBlock &MBB) const {  in getSaluInsertionAtEnd()
786   auto InsertionPt = MBB.getFirstTerminator();  in getSaluInsertionAtEnd()
788   for (auto I = InsertionPt, E = MBB.end(); I != E; ++I) {  in getSaluInsertionAtEnd()
798   while (InsertionPt != MBB.begin()) {  in getSaluInsertionAtEnd()
818   for (MachineBasicBlock &MBB : *MF) {  in getCandidatesForLowering()
819     for (MachineInstr &MI : MBB.phis()) {  in getCandidatesForLowering()
849                                         MachineBasicBlock *MBB) {  in replaceDstReg()  argument
853 void Vreg1LoweringHelper::buildMergeLaneMasks(MachineBasicBlock &MBB,  in buildMergeLaneMasks()  argument
865       BuildMI(MBB, I, DL, TII->get(AMDGPU::COPY), DstReg).addReg(CurReg);  in buildMergeLaneMasks()
867       BuildMI(MBB, I, DL, TII->get(AMDGPU::COPY), DstReg).addReg(ExecReg);  in buildMergeLaneMasks()
869       BuildMI(MBB, I, DL, TII->get(XorOp), DstReg)  in buildMergeLaneMasks()
883       BuildMI(MBB, I, DL, TII->get(AndN2Op), PrevMaskedReg)  in buildMergeLaneMasks()
894       BuildMI(MBB, I, DL, TII->get(AndOp), CurMaskedReg)  in buildMergeLaneMasks()
901     BuildMI(MBB, I, DL, TII->get(AMDGPU::COPY), DstReg)  in buildMergeLaneMasks()
904     BuildMI(MBB, I, DL, TII->get(AMDGPU::COPY), DstReg)  in buildMergeLaneMasks()
907     BuildMI(MBB, I, DL, TII->get(OrN2Op), DstReg)  in buildMergeLaneMasks()
911     BuildMI(MBB, I, DL, TII->get(OrOp), DstReg)  in buildMergeLaneMasks()