16 /// by writing to the 64-bit EXEC register (each bit corresponds to a
18 /// to its bit of the VCC register (like EXEC VCC is 64-bits, one for each
20 /// EXEC to update the predicates.
32 /// %sgpr0 = S_AND_SAVEEXEC_B64 %vcc  // Save and update the exec mask
33 /// %sgpr0 = S_XOR_B64 %sgpr0, %exec  // Clear live bits from saved exec mask
37 ///                                   // EXEC are zero.
41 /// %sgpr0 = S_OR_SAVEEXEC_B64 %sgpr0  // Restore the exec mask for the Then
43 /// %exec = S_XOR_B64 %sgpr0, %exec    // Update the exec mask
48 /// %exec = S_OR_B64 %exec, %sgpr0     // Re-enable saved exec mask bits
93   unsigned Exec;  member in __anon0c226a110111::SILowerControlFlow
218   // If there is only one use of save exec register and that use is SI_END_CF,  in emitIf()
219   // we can optimize SI_IF by returning the full saved exec mask instead of  in emitIf()
230   // Add an implicit def of exec to discourage scheduling VALU after this which  in emitIf()
236     .addReg(Exec)  in emitIf()
237     .addReg(Exec, RegState::ImplicitDefine);  in emitIf()
263     BuildMI(MBB, I, DL, TII->get(MovTermOpc), Exec)  in emitIf()
293   LIS->removeAllRegUnitsForPhysReg(AMDGPU::EXEC);  in emitIf()
319     .add(MI.getOperand(1)); // Saved EXEC  in emitElse()
327   // This accounts for any modification of the EXEC mask within the block and  in emitElse()
330                           .addReg(Exec)  in emitElse()
334     BuildMI(MBB, ElsePt, DL, TII->get(XorTermrOpc), Exec)  in emitElse()
335     .addReg(Exec)  in emitElse()
365   LIS->removeAllRegUnitsForPhysReg(AMDGPU::EXEC);  in emitElse()
373   // Skip ANDing with exec if the break condition is already masked by exec  in emitIfBreak()
385   // AND the break condition operand with exec, then OR that into the "loop  in emitIfBreak()
392              .addReg(Exec)  in emitIfBreak()
427       BuildMI(MBB, &MI, DL, TII->get(Andn2TermOpc), Exec)  in emitLoop()
428           .addReg(Exec)  in emitLoop()
513     BuildMI(MBB, InsPt, DL, TII->get(Opcode), Exec)  in emitEndCf()
514     .addReg(Exec)  in emitEndCf()
564 // for exec or two operands if source was another equivalent operation.
578   // Make sure we do not modify exec between def and use.  in findMaskOperands()
579   // A copy with implicitly defined exec inserted earlier is an exclusion, it  in findMaskOperands()
580   // does not really modify exec.  in findMaskOperands()
582     if (I->modifiesRegister(AMDGPU::EXEC, TRI) &&  in findMaskOperands()
583         !(I->isCopy() && I->getOperand(0).getReg() != Exec))  in findMaskOperands()
588         (SrcOp.getReg().isVirtual() || SrcOp.getReg() == Exec))  in findMaskOperands()
595 // One of the operands is exec mask.
601   if (Ops.size() == 1) OpToReplace = 2; // First operand can be exec or its copy  in combineMasks()
620   // END_CF in the only successor we can avoid emitting exec mask restore here.  in optimizeEndCf()
634     assert(SavedExec.isVirtual() && "Expected saved exec to be src1!");  in optimizeEndCf()
698       // Cleanup bit manipulations on exec mask  in process()
783     Exec = AMDGPU::EXEC_LO;  in runOnMachineFunction()
793     Exec = AMDGPU::EXEC;  in runOnMachineFunction()