112     unsigned Width;  member
809   Width = getOpcodeWidth(*I, *LSO.TII);  in setMI()
1031     if (getBufferFormatWithCompCount(CI.Format, CI.Width + Paired.Width, STI) == 0)  in offsetsCanBeCombined()
1042     if (EltOffset0 + CI.Width != EltOffset1 &&  in offsetsCanBeCombined()
1043             EltOffset1 + Paired.Width != EltOffset0)  in offsetsCanBeCombined()
1054       if (CI.Width != Paired.Width &&  in offsetsCanBeCombined()
1055           (CI.Width < Paired.Width) == (CI.Offset < Paired.Offset))  in offsetsCanBeCombined()
1123   const unsigned Width = (CI.Width + Paired.Width);  in widthsFit()  local
1126     return (Width <= 4) && (STM.hasDwordx3LoadStores() || (Width != 3));  in widthsFit()
1130     switch (Width) {  in widthsFit()
1561       getBufferFormatWithCompCount(CI.Format, CI.Width + Paired.Width, *STM);  in mergeTBufferLoadPair()
1604       getBufferFormatWithCompCount(CI.Format, CI.Width + Paired.Width, *STM);  in mergeTBufferStorePair()
1684   const unsigned Width = CI.Width + Paired.Width;  in getNewOpcode()  local
1691                                   Width);  in getNewOpcode()
1695                                   Width);  in getNewOpcode()
1700     switch (Width) {  in getNewOpcode()
1713     switch (Width) {  in getNewOpcode()
1730         STM->isXNACKEnabled() && MMO->getAlign().value() < Width * 4;  in getNewOpcode()
1731     switch (Width) {  in getNewOpcode()
1749     switch (Width) {  in getNewOpcode()
1760     switch (Width) {  in getNewOpcode()
1771     switch (Width) {  in getNewOpcode()
1782     switch (Width) {  in getNewOpcode()
1793     switch (Width) {  in getNewOpcode()
1804     switch (Width) {  in getNewOpcode()
1815     assert(((unsigned)llvm::popcount(CI.DMask | Paired.DMask) == Width) &&  in getNewOpcode()
1817     return AMDGPU::getMaskedMIMGOp(CI.I->getOpcode(), Width);  in getNewOpcode()
1826            CI.Width + Paired.Width)) &&  in getSubRegIdxs()
1840   assert(CI.Width >= 1 && CI.Width <= 4);  in getSubRegIdxs()
1841   assert(Paired.Width >= 1 && Paired.Width <= 4);  in getSubRegIdxs()
1844     Idx1 = Idxs[0][Paired.Width - 1];  in getSubRegIdxs()
1845     Idx0 = Idxs[Paired.Width][CI.Width - 1];  in getSubRegIdxs()
1847     Idx0 = Idxs[0][CI.Width - 1];  in getSubRegIdxs()
1848     Idx1 = Idxs[CI.Width][Paired.Width - 1];  in getSubRegIdxs()
1859     switch (CI.Width + Paired.Width) {  in getTargetRegisterClass()
1875   unsigned BitWidth = 32 * (CI.Width + Paired.Width);  in getTargetRegisterClass()
2416       OptimizeListAgain |= CI.Width + Paired.Width < 8;  in optimizeInstsWithSameBaseAddr()
2420       OptimizeListAgain |= CI.Width + Paired.Width < 4;  in optimizeInstsWithSameBaseAddr()
2424       OptimizeListAgain |= CI.Width + Paired.Width < 4;  in optimizeInstsWithSameBaseAddr()
2428       OptimizeListAgain |= CI.Width + Paired.Width < 4;  in optimizeInstsWithSameBaseAddr()
2432       OptimizeListAgain |= CI.Width + Paired.Width < 4;  in optimizeInstsWithSameBaseAddr()
2436       OptimizeListAgain |= CI.Width + Paired.Width < 4;  in optimizeInstsWithSameBaseAddr()
2442       OptimizeListAgain |= CI.Width + Paired.Width < 4;  in optimizeInstsWithSameBaseAddr()
2448       OptimizeListAgain |= CI.Width + Paired.Width < 4;  in optimizeInstsWithSameBaseAddr()