116     InstClassEnum InstClass;  member
182       return (InstClass == MIMG) ? DMask < Other.DMask : Offset < Other.Offset;  in operator <()
647   assert(CI.InstClass == Paired.InstClass);  in getCommonInstClass()
649   if ((CI.InstClass == FLAT_LOAD || CI.InstClass == FLAT_STORE) &&  in getCommonInstClass()
651     return (CI.InstClass == FLAT_STORE) ? GLOBAL_STORE : GLOBAL_LOAD;  in getCommonInstClass()
653   return CI.InstClass;  in getCommonInstClass()
769   InstClass = getInstClass(Opc, *LSO.TII);  in setMI()
771   if (InstClass == UNKNOWN)  in setMI()
776   switch (InstClass) {  in setMI()
797   if (InstClass == MIMG) {  in setMI()
806   if (InstClass == TBUFFER_LOAD || InstClass == TBUFFER_STORE)  in setMI()
811   if ((InstClass == DS_READ) || (InstClass == DS_WRITE)) {  in setMI()
813   } else if (InstClass != MIMG) {  in setMI()
924   assert(CI.InstClass == MIMG);  in dmasksCanBeCombined()
1000   assert(CI.InstClass != MIMG);  in offsetsCanBeCombined()
1011   if (CI.InstClass == TBUFFER_LOAD || CI.InstClass == TBUFFER_STORE) {  in offsetsCanBeCombined()
1041   if ((CI.InstClass != DS_READ) && (CI.InstClass != DS_WRITE)) {  in offsetsCanBeCombined()
1047     if (CI.InstClass == S_LOAD_IMM || CI.InstClass == S_BUFFER_LOAD_IMM ||  in offsetsCanBeCombined()
1048         CI.InstClass == S_BUFFER_LOAD_SGPR_IMM) {  in offsetsCanBeCombined()
1124   switch (CI.InstClass) {  in widthsFit()
1170   if (CI.InstClass == UNKNOWN || Paired.InstClass == UNKNOWN)  in checkAndPrepareMerge()
1172   assert(CI.InstClass == Paired.InstClass);  in checkAndPrepareMerge()
1180   if (CI.InstClass == MIMG) {  in checkAndPrepareMerge()
1213   if (CI.InstClass == DS_READ || CI.InstClass == DS_WRITE)  in checkAndPrepareMerge()
1486   if (CI.InstClass == S_BUFFER_LOAD_SGPR_IMM)  in mergeSMemLoadImmPair()
1688     assert(CI.InstClass == BUFFER_LOAD || CI.InstClass == BUFFER_STORE);  in getNewOpcode()
1824   assert((CI.InstClass != MIMG ||  in getSubRegIdxs()
1857   if (CI.InstClass == S_BUFFER_LOAD_IMM ||  in getTargetRegisterClass()
1858       CI.InstClass == S_BUFFER_LOAD_SGPR_IMM || CI.InstClass == S_LOAD_IMM) {  in getTargetRegisterClass()
2234     if (AddrList.front().InstClass == CI.InstClass &&  in addInstToMergeableList()
2274     const InstClassEnum InstClass = getInstClass(MI.getOpcode(), *TII);  in collectMergeableInsts()  local
2275     if (InstClass == UNKNOWN)  in collectMergeableInsts()
2291     if (CI.InstClass == DS_WRITE && CI.IsAGPR) {  in collectMergeableInsts()
2402     switch (CI.InstClass) {  in optimizeInstsWithSameBaseAddr()