Lines Matching refs:AddrReg
121 const MachineOperand *AddrReg[MaxAddressRegs]; member
133 if (AddrReg[i]->isImm() || AddrRegNext.isImm()) { in hasSameBaseAddress()
134 if (AddrReg[i]->isImm() != AddrRegNext.isImm() || in hasSameBaseAddress()
135 AddrReg[i]->getImm() != AddrRegNext.getImm()) { in hasSameBaseAddress()
143 if (AddrReg[i]->getReg() != AddrRegNext.getReg() || in hasSameBaseAddress()
144 AddrReg[i]->getSubReg() != AddrRegNext.getSubReg()) { in hasSameBaseAddress()
153 const MachineOperand *AddrOp = AddrReg[i]; in hasMergeableAddress()
848 AddrReg[J] = &I->getOperand(AddrIdx[J]); in setMI()
1296 const auto *AddrReg = TII->getNamedOperand(*CI.I, AMDGPU::OpName::addr); in mergeRead2Pair() local
1313 Register BaseReg = AddrReg->getReg(); in mergeRead2Pair()
1314 unsigned BaseSubReg = AddrReg->getSubReg(); in mergeRead2Pair()
1326 .addReg(AddrReg->getReg(), 0, BaseSubReg) in mergeRead2Pair()
1371 const MachineOperand *AddrReg = in mergeWrite2Pair() local
1395 Register BaseReg = AddrReg->getReg(); in mergeWrite2Pair()
1396 unsigned BaseSubReg = AddrReg->getSubReg(); in mergeWrite2Pair()
1408 .addReg(AddrReg->getReg(), 0, BaseSubReg) in mergeWrite2Pair()