Lines Matching refs:AMDGPU
167 AddrOp->getReg() != AMDGPU::SGPR_NULL) in hasMergeableAddress()
331 return AMDGPU::getMUBUFElements(Opc); in getOpcodeWidth()
335 TII.getNamedOperand(MI, AMDGPU::OpName::dmask)->getImm(); in getOpcodeWidth()
339 return AMDGPU::getMTBUFElements(Opc); in getOpcodeWidth()
343 case AMDGPU::S_BUFFER_LOAD_DWORD_IMM: in getOpcodeWidth()
344 case AMDGPU::S_BUFFER_LOAD_DWORD_SGPR_IMM: in getOpcodeWidth()
345 case AMDGPU::S_LOAD_DWORD_IMM: in getOpcodeWidth()
346 case AMDGPU::GLOBAL_LOAD_DWORD: in getOpcodeWidth()
347 case AMDGPU::GLOBAL_LOAD_DWORD_SADDR: in getOpcodeWidth()
348 case AMDGPU::GLOBAL_STORE_DWORD: in getOpcodeWidth()
349 case AMDGPU::GLOBAL_STORE_DWORD_SADDR: in getOpcodeWidth()
350 case AMDGPU::FLAT_LOAD_DWORD: in getOpcodeWidth()
351 case AMDGPU::FLAT_STORE_DWORD: in getOpcodeWidth()
353 case AMDGPU::S_BUFFER_LOAD_DWORDX2_IMM: in getOpcodeWidth()
354 case AMDGPU::S_BUFFER_LOAD_DWORDX2_SGPR_IMM: in getOpcodeWidth()
355 case AMDGPU::S_LOAD_DWORDX2_IMM: in getOpcodeWidth()
356 case AMDGPU::S_LOAD_DWORDX2_IMM_ec: in getOpcodeWidth()
357 case AMDGPU::GLOBAL_LOAD_DWORDX2: in getOpcodeWidth()
358 case AMDGPU::GLOBAL_LOAD_DWORDX2_SADDR: in getOpcodeWidth()
359 case AMDGPU::GLOBAL_STORE_DWORDX2: in getOpcodeWidth()
360 case AMDGPU::GLOBAL_STORE_DWORDX2_SADDR: in getOpcodeWidth()
361 case AMDGPU::FLAT_LOAD_DWORDX2: in getOpcodeWidth()
362 case AMDGPU::FLAT_STORE_DWORDX2: in getOpcodeWidth()
364 case AMDGPU::S_BUFFER_LOAD_DWORDX3_IMM: in getOpcodeWidth()
365 case AMDGPU::S_BUFFER_LOAD_DWORDX3_SGPR_IMM: in getOpcodeWidth()
366 case AMDGPU::S_LOAD_DWORDX3_IMM: in getOpcodeWidth()
367 case AMDGPU::S_LOAD_DWORDX3_IMM_ec: in getOpcodeWidth()
368 case AMDGPU::GLOBAL_LOAD_DWORDX3: in getOpcodeWidth()
369 case AMDGPU::GLOBAL_LOAD_DWORDX3_SADDR: in getOpcodeWidth()
370 case AMDGPU::GLOBAL_STORE_DWORDX3: in getOpcodeWidth()
371 case AMDGPU::GLOBAL_STORE_DWORDX3_SADDR: in getOpcodeWidth()
372 case AMDGPU::FLAT_LOAD_DWORDX3: in getOpcodeWidth()
373 case AMDGPU::FLAT_STORE_DWORDX3: in getOpcodeWidth()
375 case AMDGPU::S_BUFFER_LOAD_DWORDX4_IMM: in getOpcodeWidth()
376 case AMDGPU::S_BUFFER_LOAD_DWORDX4_SGPR_IMM: in getOpcodeWidth()
377 case AMDGPU::S_LOAD_DWORDX4_IMM: in getOpcodeWidth()
378 case AMDGPU::S_LOAD_DWORDX4_IMM_ec: in getOpcodeWidth()
379 case AMDGPU::GLOBAL_LOAD_DWORDX4: in getOpcodeWidth()
380 case AMDGPU::GLOBAL_LOAD_DWORDX4_SADDR: in getOpcodeWidth()
381 case AMDGPU::GLOBAL_STORE_DWORDX4: in getOpcodeWidth()
382 case AMDGPU::GLOBAL_STORE_DWORDX4_SADDR: in getOpcodeWidth()
383 case AMDGPU::FLAT_LOAD_DWORDX4: in getOpcodeWidth()
384 case AMDGPU::FLAT_STORE_DWORDX4: in getOpcodeWidth()
386 case AMDGPU::S_BUFFER_LOAD_DWORDX8_IMM: in getOpcodeWidth()
387 case AMDGPU::S_BUFFER_LOAD_DWORDX8_SGPR_IMM: in getOpcodeWidth()
388 case AMDGPU::S_LOAD_DWORDX8_IMM: in getOpcodeWidth()
389 case AMDGPU::S_LOAD_DWORDX8_IMM_ec: in getOpcodeWidth()
391 case AMDGPU::DS_READ_B32: in getOpcodeWidth()
392 case AMDGPU::DS_READ_B32_gfx9: in getOpcodeWidth()
393 case AMDGPU::DS_WRITE_B32: in getOpcodeWidth()
394 case AMDGPU::DS_WRITE_B32_gfx9: in getOpcodeWidth()
396 case AMDGPU::DS_READ_B64: in getOpcodeWidth()
397 case AMDGPU::DS_READ_B64_gfx9: in getOpcodeWidth()
398 case AMDGPU::DS_WRITE_B64: in getOpcodeWidth()
399 case AMDGPU::DS_WRITE_B64_gfx9: in getOpcodeWidth()
411 switch (AMDGPU::getMUBUFBaseOpcode(Opc)) { in getInstClass()
414 case AMDGPU::BUFFER_LOAD_DWORD_BOTHEN: in getInstClass()
415 case AMDGPU::BUFFER_LOAD_DWORD_BOTHEN_exact: in getInstClass()
416 case AMDGPU::BUFFER_LOAD_DWORD_IDXEN: in getInstClass()
417 case AMDGPU::BUFFER_LOAD_DWORD_IDXEN_exact: in getInstClass()
418 case AMDGPU::BUFFER_LOAD_DWORD_OFFEN: in getInstClass()
419 case AMDGPU::BUFFER_LOAD_DWORD_OFFEN_exact: in getInstClass()
420 case AMDGPU::BUFFER_LOAD_DWORD_OFFSET: in getInstClass()
421 case AMDGPU::BUFFER_LOAD_DWORD_OFFSET_exact: in getInstClass()
422 case AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_BOTHEN: in getInstClass()
423 case AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_BOTHEN_exact: in getInstClass()
424 case AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_IDXEN: in getInstClass()
425 case AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_IDXEN_exact: in getInstClass()
426 case AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFEN: in getInstClass()
427 case AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFEN_exact: in getInstClass()
428 case AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFSET: in getInstClass()
429 case AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFSET_exact: in getInstClass()
431 case AMDGPU::BUFFER_STORE_DWORD_BOTHEN: in getInstClass()
432 case AMDGPU::BUFFER_STORE_DWORD_BOTHEN_exact: in getInstClass()
433 case AMDGPU::BUFFER_STORE_DWORD_IDXEN: in getInstClass()
434 case AMDGPU::BUFFER_STORE_DWORD_IDXEN_exact: in getInstClass()
435 case AMDGPU::BUFFER_STORE_DWORD_OFFEN: in getInstClass()
436 case AMDGPU::BUFFER_STORE_DWORD_OFFEN_exact: in getInstClass()
437 case AMDGPU::BUFFER_STORE_DWORD_OFFSET: in getInstClass()
438 case AMDGPU::BUFFER_STORE_DWORD_OFFSET_exact: in getInstClass()
439 case AMDGPU::BUFFER_STORE_DWORD_VBUFFER_BOTHEN: in getInstClass()
440 case AMDGPU::BUFFER_STORE_DWORD_VBUFFER_BOTHEN_exact: in getInstClass()
441 case AMDGPU::BUFFER_STORE_DWORD_VBUFFER_IDXEN: in getInstClass()
442 case AMDGPU::BUFFER_STORE_DWORD_VBUFFER_IDXEN_exact: in getInstClass()
443 case AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFEN: in getInstClass()
444 case AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFEN_exact: in getInstClass()
445 case AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFSET: in getInstClass()
446 case AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFSET_exact: in getInstClass()
452 if (!AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::vaddr) && in getInstClass()
453 !AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::vaddr0)) in getInstClass()
456 if (AMDGPU::getMIMGBaseOpcode(Opc)->BVH) in getInstClass()
465 switch (AMDGPU::getMTBUFBaseOpcode(Opc)) { in getInstClass()
468 case AMDGPU::TBUFFER_LOAD_FORMAT_X_BOTHEN: in getInstClass()
469 case AMDGPU::TBUFFER_LOAD_FORMAT_X_BOTHEN_exact: in getInstClass()
470 case AMDGPU::TBUFFER_LOAD_FORMAT_X_IDXEN: in getInstClass()
471 case AMDGPU::TBUFFER_LOAD_FORMAT_X_IDXEN_exact: in getInstClass()
472 case AMDGPU::TBUFFER_LOAD_FORMAT_X_OFFEN: in getInstClass()
473 case AMDGPU::TBUFFER_LOAD_FORMAT_X_OFFEN_exact: in getInstClass()
474 case AMDGPU::TBUFFER_LOAD_FORMAT_X_OFFSET: in getInstClass()
475 case AMDGPU::TBUFFER_LOAD_FORMAT_X_OFFSET_exact: in getInstClass()
476 case AMDGPU::TBUFFER_LOAD_FORMAT_X_VBUFFER_BOTHEN: in getInstClass()
477 case AMDGPU::TBUFFER_LOAD_FORMAT_X_VBUFFER_BOTHEN_exact: in getInstClass()
478 case AMDGPU::TBUFFER_LOAD_FORMAT_X_VBUFFER_IDXEN: in getInstClass()
479 case AMDGPU::TBUFFER_LOAD_FORMAT_X_VBUFFER_IDXEN_exact: in getInstClass()
480 case AMDGPU::TBUFFER_LOAD_FORMAT_X_VBUFFER_OFFEN: in getInstClass()
481 case AMDGPU::TBUFFER_LOAD_FORMAT_X_VBUFFER_OFFEN_exact: in getInstClass()
482 case AMDGPU::TBUFFER_LOAD_FORMAT_X_VBUFFER_OFFSET: in getInstClass()
483 case AMDGPU::TBUFFER_LOAD_FORMAT_X_VBUFFER_OFFSET_exact: in getInstClass()
485 case AMDGPU::TBUFFER_STORE_FORMAT_X_OFFEN: in getInstClass()
486 case AMDGPU::TBUFFER_STORE_FORMAT_X_OFFEN_exact: in getInstClass()
487 case AMDGPU::TBUFFER_STORE_FORMAT_X_OFFSET: in getInstClass()
488 case AMDGPU::TBUFFER_STORE_FORMAT_X_OFFSET_exact: in getInstClass()
489 case AMDGPU::TBUFFER_STORE_FORMAT_X_VBUFFER_OFFEN: in getInstClass()
490 case AMDGPU::TBUFFER_STORE_FORMAT_X_VBUFFER_OFFEN_exact: in getInstClass()
491 case AMDGPU::TBUFFER_STORE_FORMAT_X_VBUFFER_OFFSET: in getInstClass()
492 case AMDGPU::TBUFFER_STORE_FORMAT_X_VBUFFER_OFFSET_exact: in getInstClass()
497 case AMDGPU::S_BUFFER_LOAD_DWORD_IMM: in getInstClass()
498 case AMDGPU::S_BUFFER_LOAD_DWORDX2_IMM: in getInstClass()
499 case AMDGPU::S_BUFFER_LOAD_DWORDX3_IMM: in getInstClass()
500 case AMDGPU::S_BUFFER_LOAD_DWORDX4_IMM: in getInstClass()
501 case AMDGPU::S_BUFFER_LOAD_DWORDX8_IMM: in getInstClass()
503 case AMDGPU::S_BUFFER_LOAD_DWORD_SGPR_IMM: in getInstClass()
504 case AMDGPU::S_BUFFER_LOAD_DWORDX2_SGPR_IMM: in getInstClass()
505 case AMDGPU::S_BUFFER_LOAD_DWORDX3_SGPR_IMM: in getInstClass()
506 case AMDGPU::S_BUFFER_LOAD_DWORDX4_SGPR_IMM: in getInstClass()
507 case AMDGPU::S_BUFFER_LOAD_DWORDX8_SGPR_IMM: in getInstClass()
509 case AMDGPU::S_LOAD_DWORD_IMM: in getInstClass()
510 case AMDGPU::S_LOAD_DWORDX2_IMM: in getInstClass()
511 case AMDGPU::S_LOAD_DWORDX3_IMM: in getInstClass()
512 case AMDGPU::S_LOAD_DWORDX4_IMM: in getInstClass()
513 case AMDGPU::S_LOAD_DWORDX8_IMM: in getInstClass()
514 case AMDGPU::S_LOAD_DWORDX2_IMM_ec: in getInstClass()
515 case AMDGPU::S_LOAD_DWORDX3_IMM_ec: in getInstClass()
516 case AMDGPU::S_LOAD_DWORDX4_IMM_ec: in getInstClass()
517 case AMDGPU::S_LOAD_DWORDX8_IMM_ec: in getInstClass()
519 case AMDGPU::DS_READ_B32: in getInstClass()
520 case AMDGPU::DS_READ_B32_gfx9: in getInstClass()
521 case AMDGPU::DS_READ_B64: in getInstClass()
522 case AMDGPU::DS_READ_B64_gfx9: in getInstClass()
524 case AMDGPU::DS_WRITE_B32: in getInstClass()
525 case AMDGPU::DS_WRITE_B32_gfx9: in getInstClass()
526 case AMDGPU::DS_WRITE_B64: in getInstClass()
527 case AMDGPU::DS_WRITE_B64_gfx9: in getInstClass()
529 case AMDGPU::GLOBAL_LOAD_DWORD: in getInstClass()
530 case AMDGPU::GLOBAL_LOAD_DWORDX2: in getInstClass()
531 case AMDGPU::GLOBAL_LOAD_DWORDX3: in getInstClass()
532 case AMDGPU::GLOBAL_LOAD_DWORDX4: in getInstClass()
533 case AMDGPU::FLAT_LOAD_DWORD: in getInstClass()
534 case AMDGPU::FLAT_LOAD_DWORDX2: in getInstClass()
535 case AMDGPU::FLAT_LOAD_DWORDX3: in getInstClass()
536 case AMDGPU::FLAT_LOAD_DWORDX4: in getInstClass()
538 case AMDGPU::GLOBAL_LOAD_DWORD_SADDR: in getInstClass()
539 case AMDGPU::GLOBAL_LOAD_DWORDX2_SADDR: in getInstClass()
540 case AMDGPU::GLOBAL_LOAD_DWORDX3_SADDR: in getInstClass()
541 case AMDGPU::GLOBAL_LOAD_DWORDX4_SADDR: in getInstClass()
543 case AMDGPU::GLOBAL_STORE_DWORD: in getInstClass()
544 case AMDGPU::GLOBAL_STORE_DWORDX2: in getInstClass()
545 case AMDGPU::GLOBAL_STORE_DWORDX3: in getInstClass()
546 case AMDGPU::GLOBAL_STORE_DWORDX4: in getInstClass()
547 case AMDGPU::FLAT_STORE_DWORD: in getInstClass()
548 case AMDGPU::FLAT_STORE_DWORDX2: in getInstClass()
549 case AMDGPU::FLAT_STORE_DWORDX3: in getInstClass()
550 case AMDGPU::FLAT_STORE_DWORDX4: in getInstClass()
552 case AMDGPU::GLOBAL_STORE_DWORD_SADDR: in getInstClass()
553 case AMDGPU::GLOBAL_STORE_DWORDX2_SADDR: in getInstClass()
554 case AMDGPU::GLOBAL_STORE_DWORDX3_SADDR: in getInstClass()
555 case AMDGPU::GLOBAL_STORE_DWORDX4_SADDR: in getInstClass()
567 return AMDGPU::getMUBUFBaseOpcode(Opc); in getInstSubclass()
569 const AMDGPU::MIMGInfo *Info = AMDGPU::getMIMGInfo(Opc); in getInstSubclass()
574 return AMDGPU::getMTBUFBaseOpcode(Opc); in getInstSubclass()
576 case AMDGPU::DS_READ_B32: in getInstSubclass()
577 case AMDGPU::DS_READ_B32_gfx9: in getInstSubclass()
578 case AMDGPU::DS_READ_B64: in getInstSubclass()
579 case AMDGPU::DS_READ_B64_gfx9: in getInstSubclass()
580 case AMDGPU::DS_WRITE_B32: in getInstSubclass()
581 case AMDGPU::DS_WRITE_B32_gfx9: in getInstSubclass()
582 case AMDGPU::DS_WRITE_B64: in getInstSubclass()
583 case AMDGPU::DS_WRITE_B64_gfx9: in getInstSubclass()
585 case AMDGPU::S_BUFFER_LOAD_DWORD_IMM: in getInstSubclass()
586 case AMDGPU::S_BUFFER_LOAD_DWORDX2_IMM: in getInstSubclass()
587 case AMDGPU::S_BUFFER_LOAD_DWORDX3_IMM: in getInstSubclass()
588 case AMDGPU::S_BUFFER_LOAD_DWORDX4_IMM: in getInstSubclass()
589 case AMDGPU::S_BUFFER_LOAD_DWORDX8_IMM: in getInstSubclass()
590 return AMDGPU::S_BUFFER_LOAD_DWORD_IMM; in getInstSubclass()
591 case AMDGPU::S_BUFFER_LOAD_DWORD_SGPR_IMM: in getInstSubclass()
592 case AMDGPU::S_BUFFER_LOAD_DWORDX2_SGPR_IMM: in getInstSubclass()
593 case AMDGPU::S_BUFFER_LOAD_DWORDX3_SGPR_IMM: in getInstSubclass()
594 case AMDGPU::S_BUFFER_LOAD_DWORDX4_SGPR_IMM: in getInstSubclass()
595 case AMDGPU::S_BUFFER_LOAD_DWORDX8_SGPR_IMM: in getInstSubclass()
596 return AMDGPU::S_BUFFER_LOAD_DWORD_SGPR_IMM; in getInstSubclass()
597 case AMDGPU::S_LOAD_DWORD_IMM: in getInstSubclass()
598 case AMDGPU::S_LOAD_DWORDX2_IMM: in getInstSubclass()
599 case AMDGPU::S_LOAD_DWORDX3_IMM: in getInstSubclass()
600 case AMDGPU::S_LOAD_DWORDX4_IMM: in getInstSubclass()
601 case AMDGPU::S_LOAD_DWORDX8_IMM: in getInstSubclass()
602 case AMDGPU::S_LOAD_DWORDX2_IMM_ec: in getInstSubclass()
603 case AMDGPU::S_LOAD_DWORDX3_IMM_ec: in getInstSubclass()
604 case AMDGPU::S_LOAD_DWORDX4_IMM_ec: in getInstSubclass()
605 case AMDGPU::S_LOAD_DWORDX8_IMM_ec: in getInstSubclass()
606 return AMDGPU::S_LOAD_DWORD_IMM; in getInstSubclass()
607 case AMDGPU::GLOBAL_LOAD_DWORD: in getInstSubclass()
608 case AMDGPU::GLOBAL_LOAD_DWORDX2: in getInstSubclass()
609 case AMDGPU::GLOBAL_LOAD_DWORDX3: in getInstSubclass()
610 case AMDGPU::GLOBAL_LOAD_DWORDX4: in getInstSubclass()
611 case AMDGPU::FLAT_LOAD_DWORD: in getInstSubclass()
612 case AMDGPU::FLAT_LOAD_DWORDX2: in getInstSubclass()
613 case AMDGPU::FLAT_LOAD_DWORDX3: in getInstSubclass()
614 case AMDGPU::FLAT_LOAD_DWORDX4: in getInstSubclass()
615 return AMDGPU::FLAT_LOAD_DWORD; in getInstSubclass()
616 case AMDGPU::GLOBAL_LOAD_DWORD_SADDR: in getInstSubclass()
617 case AMDGPU::GLOBAL_LOAD_DWORDX2_SADDR: in getInstSubclass()
618 case AMDGPU::GLOBAL_LOAD_DWORDX3_SADDR: in getInstSubclass()
619 case AMDGPU::GLOBAL_LOAD_DWORDX4_SADDR: in getInstSubclass()
620 return AMDGPU::GLOBAL_LOAD_DWORD_SADDR; in getInstSubclass()
621 case AMDGPU::GLOBAL_STORE_DWORD: in getInstSubclass()
622 case AMDGPU::GLOBAL_STORE_DWORDX2: in getInstSubclass()
623 case AMDGPU::GLOBAL_STORE_DWORDX3: in getInstSubclass()
624 case AMDGPU::GLOBAL_STORE_DWORDX4: in getInstSubclass()
625 case AMDGPU::FLAT_STORE_DWORD: in getInstSubclass()
626 case AMDGPU::FLAT_STORE_DWORDX2: in getInstSubclass()
627 case AMDGPU::FLAT_STORE_DWORDX3: in getInstSubclass()
628 case AMDGPU::FLAT_STORE_DWORDX4: in getInstSubclass()
629 return AMDGPU::FLAT_STORE_DWORD; in getInstSubclass()
630 case AMDGPU::GLOBAL_STORE_DWORD_SADDR: in getInstSubclass()
631 case AMDGPU::GLOBAL_STORE_DWORDX2_SADDR: in getInstSubclass()
632 case AMDGPU::GLOBAL_STORE_DWORDX3_SADDR: in getInstSubclass()
633 case AMDGPU::GLOBAL_STORE_DWORDX4_SADDR: in getInstSubclass()
634 return AMDGPU::GLOBAL_STORE_DWORD_SADDR; in getInstSubclass()
660 if (AMDGPU::getMUBUFHasVAddr(Opc)) in getRegs()
662 if (AMDGPU::getMUBUFHasSrsrc(Opc)) in getRegs()
664 if (AMDGPU::getMUBUFHasSoffset(Opc)) in getRegs()
671 int VAddr0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vaddr0); in getRegs()
674 TII.isMIMG(Opc) ? AMDGPU::OpName::srsrc : AMDGPU::OpName::rsrc; in getRegs()
675 int RsrcIdx = AMDGPU::getNamedOperandIdx(Opc, RsrcName); in getRegs()
681 const AMDGPU::MIMGInfo *Info = AMDGPU::getMIMGInfo(Opc); in getRegs()
682 if (Info && AMDGPU::getMIMGBaseOpcodeInfo(Info->BaseOpcode)->Sampler) in getRegs()
688 if (AMDGPU::getMTBUFHasVAddr(Opc)) in getRegs()
690 if (AMDGPU::getMTBUFHasSrsrc(Opc)) in getRegs()
692 if (AMDGPU::getMTBUFHasSoffset(Opc)) in getRegs()
701 case AMDGPU::S_BUFFER_LOAD_DWORD_SGPR_IMM: in getRegs()
702 case AMDGPU::S_BUFFER_LOAD_DWORDX2_SGPR_IMM: in getRegs()
703 case AMDGPU::S_BUFFER_LOAD_DWORDX3_SGPR_IMM: in getRegs()
704 case AMDGPU::S_BUFFER_LOAD_DWORDX4_SGPR_IMM: in getRegs()
705 case AMDGPU::S_BUFFER_LOAD_DWORDX8_SGPR_IMM: in getRegs()
708 case AMDGPU::S_BUFFER_LOAD_DWORD_IMM: in getRegs()
709 case AMDGPU::S_BUFFER_LOAD_DWORDX2_IMM: in getRegs()
710 case AMDGPU::S_BUFFER_LOAD_DWORDX3_IMM: in getRegs()
711 case AMDGPU::S_BUFFER_LOAD_DWORDX4_IMM: in getRegs()
712 case AMDGPU::S_BUFFER_LOAD_DWORDX8_IMM: in getRegs()
713 case AMDGPU::S_LOAD_DWORD_IMM: in getRegs()
714 case AMDGPU::S_LOAD_DWORDX2_IMM: in getRegs()
715 case AMDGPU::S_LOAD_DWORDX3_IMM: in getRegs()
716 case AMDGPU::S_LOAD_DWORDX4_IMM: in getRegs()
717 case AMDGPU::S_LOAD_DWORDX8_IMM: in getRegs()
718 case AMDGPU::S_LOAD_DWORDX2_IMM_ec: in getRegs()
719 case AMDGPU::S_LOAD_DWORDX3_IMM_ec: in getRegs()
720 case AMDGPU::S_LOAD_DWORDX4_IMM_ec: in getRegs()
721 case AMDGPU::S_LOAD_DWORDX8_IMM_ec: in getRegs()
724 case AMDGPU::DS_READ_B32: in getRegs()
725 case AMDGPU::DS_READ_B64: in getRegs()
726 case AMDGPU::DS_READ_B32_gfx9: in getRegs()
727 case AMDGPU::DS_READ_B64_gfx9: in getRegs()
728 case AMDGPU::DS_WRITE_B32: in getRegs()
729 case AMDGPU::DS_WRITE_B64: in getRegs()
730 case AMDGPU::DS_WRITE_B32_gfx9: in getRegs()
731 case AMDGPU::DS_WRITE_B64_gfx9: in getRegs()
734 case AMDGPU::GLOBAL_LOAD_DWORD_SADDR: in getRegs()
735 case AMDGPU::GLOBAL_LOAD_DWORDX2_SADDR: in getRegs()
736 case AMDGPU::GLOBAL_LOAD_DWORDX3_SADDR: in getRegs()
737 case AMDGPU::GLOBAL_LOAD_DWORDX4_SADDR: in getRegs()
738 case AMDGPU::GLOBAL_STORE_DWORD_SADDR: in getRegs()
739 case AMDGPU::GLOBAL_STORE_DWORDX2_SADDR: in getRegs()
740 case AMDGPU::GLOBAL_STORE_DWORDX3_SADDR: in getRegs()
741 case AMDGPU::GLOBAL_STORE_DWORDX4_SADDR: in getRegs()
744 case AMDGPU::GLOBAL_LOAD_DWORD: in getRegs()
745 case AMDGPU::GLOBAL_LOAD_DWORDX2: in getRegs()
746 case AMDGPU::GLOBAL_LOAD_DWORDX3: in getRegs()
747 case AMDGPU::GLOBAL_LOAD_DWORDX4: in getRegs()
748 case AMDGPU::GLOBAL_STORE_DWORD: in getRegs()
749 case AMDGPU::GLOBAL_STORE_DWORDX2: in getRegs()
750 case AMDGPU::GLOBAL_STORE_DWORDX3: in getRegs()
751 case AMDGPU::GLOBAL_STORE_DWORDX4: in getRegs()
752 case AMDGPU::FLAT_LOAD_DWORD: in getRegs()
753 case AMDGPU::FLAT_LOAD_DWORDX2: in getRegs()
754 case AMDGPU::FLAT_LOAD_DWORDX3: in getRegs()
755 case AMDGPU::FLAT_LOAD_DWORDX4: in getRegs()
756 case AMDGPU::FLAT_STORE_DWORD: in getRegs()
757 case AMDGPU::FLAT_STORE_DWORDX2: in getRegs()
758 case AMDGPU::FLAT_STORE_DWORDX3: in getRegs()
759 case AMDGPU::FLAT_STORE_DWORDX4: in getRegs()
779 (Opc == AMDGPU::DS_READ_B64 || Opc == AMDGPU::DS_READ_B64_gfx9) ? 8 in setMI()
784 (Opc == AMDGPU::DS_WRITE_B64 || Opc == AMDGPU::DS_WRITE_B64_gfx9) ? 8 in setMI()
790 EltSize = AMDGPU::convertSMRDOffsetUnits(*LSO.STM, 4); in setMI()
798 DMask = LSO.TII->getNamedOperand(*I, AMDGPU::OpName::dmask)->getImm(); in setMI()
802 int OffsetIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::offset); in setMI()
807 Format = LSO.TII->getNamedOperand(*I, AMDGPU::OpName::format)->getImm(); in setMI()
814 CPol = LSO.TII->getNamedOperand(*I, AMDGPU::OpName::cpol)->getImm(); in setMI()
823 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vaddr0) + J; in setMI()
826 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::addr); in setMI()
829 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::sbase); in setMI()
831 AddrIdx[NumAddresses++] = AMDGPU::getNamedOperandIdx( in setMI()
832 Opc, isVIMAGEorVSAMPLE ? AMDGPU::OpName::rsrc : AMDGPU::OpName::srsrc); in setMI()
835 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::soffset); in setMI()
838 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::saddr); in setMI()
841 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vaddr); in setMI()
843 AddrIdx[NumAddresses++] = AMDGPU::getNamedOperandIdx( in setMI()
844 Opc, isVIMAGEorVSAMPLE ? AMDGPU::OpName::samp : AMDGPU::OpName::ssamp); in setMI()
927 const auto *TFEOp = TII.getNamedOperand(*CI.I, AMDGPU::OpName::tfe); in dmasksCanBeCombined()
928 const auto *LWEOp = TII.getNamedOperand(*CI.I, AMDGPU::OpName::lwe); in dmasksCanBeCombined()
934 unsigned OperandsToMatch[] = {AMDGPU::OpName::cpol, AMDGPU::OpName::d16, in dmasksCanBeCombined()
935 AMDGPU::OpName::unorm, AMDGPU::OpName::da, in dmasksCanBeCombined()
936 AMDGPU::OpName::r128, AMDGPU::OpName::a16}; in dmasksCanBeCombined()
939 int Idx = AMDGPU::getNamedOperandIdx(CI.I->getOpcode(), op); in dmasksCanBeCombined()
940 if (AMDGPU::getNamedOperandIdx(Paired.I->getOpcode(), op) != Idx) in dmasksCanBeCombined()
967 const llvm::AMDGPU::GcnBufferFormatInfo *OldFormatInfo = in getBufferFormatWithCompCount()
968 llvm::AMDGPU::getGcnBufferFormatInfo(OldFormat, STI); in getBufferFormatWithCompCount()
972 const llvm::AMDGPU::GcnBufferFormatInfo *NewFormatInfo = in getBufferFormatWithCompCount()
973 llvm::AMDGPU::getGcnBufferFormatInfo(OldFormatInfo->BitsPerComp, in getBufferFormatWithCompCount()
1013 const llvm::AMDGPU::GcnBufferFormatInfo *Info0 = in offsetsCanBeCombined()
1014 llvm::AMDGPU::getGcnBufferFormatInfo(CI.Format, STI); in offsetsCanBeCombined()
1017 const llvm::AMDGPU::GcnBufferFormatInfo *Info1 = in offsetsCanBeCombined()
1018 llvm::AMDGPU::getGcnBufferFormatInfo(Paired.Format, STI); in offsetsCanBeCombined()
1145 if (const auto *Dst = TII->getNamedOperand(MI, AMDGPU::OpName::vdst)) { in getDataRegClass()
1148 if (const auto *Src = TII->getNamedOperand(MI, AMDGPU::OpName::vdata)) { in getDataRegClass()
1151 if (const auto *Src = TII->getNamedOperand(MI, AMDGPU::OpName::data0)) { in getDataRegClass()
1154 if (const auto *Dst = TII->getNamedOperand(MI, AMDGPU::OpName::sdst)) { in getDataRegClass()
1157 if (const auto *Src = TII->getNamedOperand(MI, AMDGPU::OpName::sdata)) { in getDataRegClass()
1266 BuildMI(*MBB, InsertBefore, DL, TII->get(AMDGPU::REG_SEQUENCE), SrcReg) in copyFromSrcRegs()
1277 return (EltSize == 4) ? AMDGPU::DS_READ2_B32 : AMDGPU::DS_READ2_B64; in read2Opcode()
1278 return (EltSize == 4) ? AMDGPU::DS_READ2_B32_gfx9 : AMDGPU::DS_READ2_B64_gfx9; in read2Opcode()
1283 return (EltSize == 4) ? AMDGPU::DS_READ2ST64_B32 : AMDGPU::DS_READ2ST64_B64; in read2ST64Opcode()
1285 return (EltSize == 4) ? AMDGPU::DS_READ2ST64_B32_gfx9 in read2ST64Opcode()
1286 : AMDGPU::DS_READ2ST64_B64_gfx9; in read2ST64Opcode()
1296 const auto *AddrReg = TII->getNamedOperand(*CI.I, AMDGPU::OpName::addr); in mergeRead2Pair()
1317 Register ImmReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass); in mergeRead2Pair()
1318 BuildMI(*MBB, InsertBefore, DL, TII->get(AMDGPU::S_MOV_B32), ImmReg) in mergeRead2Pair()
1321 BaseReg = MRI->createVirtualRegister(&AMDGPU::VGPR_32RegClass); in mergeRead2Pair()
1339 copyToDestRegs(CI, Paired, InsertBefore, AMDGPU::OpName::vdst, DestReg); in mergeRead2Pair()
1350 return (EltSize == 4) ? AMDGPU::DS_WRITE2_B32 : AMDGPU::DS_WRITE2_B64; in write2Opcode()
1351 return (EltSize == 4) ? AMDGPU::DS_WRITE2_B32_gfx9 in write2Opcode()
1352 : AMDGPU::DS_WRITE2_B64_gfx9; in write2Opcode()
1357 return (EltSize == 4) ? AMDGPU::DS_WRITE2ST64_B32 in write2ST64Opcode()
1358 : AMDGPU::DS_WRITE2ST64_B64; in write2ST64Opcode()
1360 return (EltSize == 4) ? AMDGPU::DS_WRITE2ST64_B32_gfx9 in write2ST64Opcode()
1361 : AMDGPU::DS_WRITE2ST64_B64_gfx9; in write2ST64Opcode()
1372 TII->getNamedOperand(*CI.I, AMDGPU::OpName::addr); in mergeWrite2Pair()
1374 TII->getNamedOperand(*CI.I, AMDGPU::OpName::data0); in mergeWrite2Pair()
1376 TII->getNamedOperand(*Paired.I, AMDGPU::OpName::data0); in mergeWrite2Pair()
1399 Register ImmReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass); in mergeWrite2Pair()
1400 BuildMI(*MBB, InsertBefore, DL, TII->get(AMDGPU::S_MOV_B32), ImmReg) in mergeWrite2Pair()
1403 BaseReg = MRI->createVirtualRegister(&AMDGPU::VGPR_32RegClass); in mergeWrite2Pair()
1442 AMDGPU::getNamedOperandIdx(CI.I->getOpcode(), AMDGPU::OpName::dmask); in mergeImagePair()
1459 copyToDestRegs(CI, Paired, InsertBefore, AMDGPU::OpName::vdata, DestReg); in mergeImagePair()
1485 .add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::sbase)); in mergeSMemLoadImmPair()
1487 New.add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::soffset)); in mergeSMemLoadImmPair()
1491 copyToDestRegs(CI, Paired, InsertBefore, AMDGPU::OpName::sdst, DestReg); in mergeSMemLoadImmPair()
1517 MIB.add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::vaddr)); in mergeBufferLoadPair()
1525 MIB.add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::srsrc)) in mergeBufferLoadPair()
1526 .add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::soffset)) in mergeBufferLoadPair()
1532 copyToDestRegs(CI, Paired, InsertBefore, AMDGPU::OpName::vdata, DestReg); in mergeBufferLoadPair()
1558 MIB.add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::vaddr)); in mergeTBufferLoadPair()
1569 MIB.add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::srsrc)) in mergeTBufferLoadPair()
1570 .add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::soffset)) in mergeTBufferLoadPair()
1577 copyToDestRegs(CI, Paired, InsertBefore, AMDGPU::OpName::vdata, DestReg); in mergeTBufferLoadPair()
1593 copyFromSrcRegs(CI, Paired, InsertBefore, AMDGPU::OpName::vdata); in mergeTBufferStorePair()
1601 MIB.add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::vaddr)); in mergeTBufferStorePair()
1612 MIB.add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::srsrc)) in mergeTBufferStorePair()
1613 .add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::soffset)) in mergeTBufferStorePair()
1638 if (auto *SAddr = TII->getNamedOperand(*CI.I, AMDGPU::OpName::saddr)) in mergeFlatLoadPair()
1642 MIB.add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::vaddr)) in mergeFlatLoadPair()
1647 copyToDestRegs(CI, Paired, InsertBefore, AMDGPU::OpName::vdst, DestReg); in mergeFlatLoadPair()
1663 copyFromSrcRegs(CI, Paired, InsertBefore, AMDGPU::OpName::vdata); in mergeFlatStorePair()
1666 .add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::vaddr)) in mergeFlatStorePair()
1669 if (auto *SAddr = TII->getNamedOperand(*CI.I, AMDGPU::OpName::saddr)) in mergeFlatStorePair()
1690 return AMDGPU::getMUBUFOpcode(AMDGPU::getMUBUFBaseOpcode(CI.I->getOpcode()), in getNewOpcode()
1694 return AMDGPU::getMTBUFOpcode(AMDGPU::getMTBUFBaseOpcode(CI.I->getOpcode()), in getNewOpcode()
1704 return AMDGPU::S_BUFFER_LOAD_DWORDX2_IMM; in getNewOpcode()
1706 return AMDGPU::S_BUFFER_LOAD_DWORDX3_IMM; in getNewOpcode()
1708 return AMDGPU::S_BUFFER_LOAD_DWORDX4_IMM; in getNewOpcode()
1710 return AMDGPU::S_BUFFER_LOAD_DWORDX8_IMM; in getNewOpcode()
1717 return AMDGPU::S_BUFFER_LOAD_DWORDX2_SGPR_IMM; in getNewOpcode()
1719 return AMDGPU::S_BUFFER_LOAD_DWORDX3_SGPR_IMM; in getNewOpcode()
1721 return AMDGPU::S_BUFFER_LOAD_DWORDX4_SGPR_IMM; in getNewOpcode()
1723 return AMDGPU::S_BUFFER_LOAD_DWORDX8_SGPR_IMM; in getNewOpcode()
1735 return NeedsConstrainedOpc ? AMDGPU::S_LOAD_DWORDX2_IMM_ec in getNewOpcode()
1736 : AMDGPU::S_LOAD_DWORDX2_IMM; in getNewOpcode()
1738 return NeedsConstrainedOpc ? AMDGPU::S_LOAD_DWORDX3_IMM_ec in getNewOpcode()
1739 : AMDGPU::S_LOAD_DWORDX3_IMM; in getNewOpcode()
1741 return NeedsConstrainedOpc ? AMDGPU::S_LOAD_DWORDX4_IMM_ec in getNewOpcode()
1742 : AMDGPU::S_LOAD_DWORDX4_IMM; in getNewOpcode()
1744 return NeedsConstrainedOpc ? AMDGPU::S_LOAD_DWORDX8_IMM_ec in getNewOpcode()
1745 : AMDGPU::S_LOAD_DWORDX8_IMM; in getNewOpcode()
1753 return AMDGPU::GLOBAL_LOAD_DWORDX2; in getNewOpcode()
1755 return AMDGPU::GLOBAL_LOAD_DWORDX3; in getNewOpcode()
1757 return AMDGPU::GLOBAL_LOAD_DWORDX4; in getNewOpcode()
1764 return AMDGPU::GLOBAL_LOAD_DWORDX2_SADDR; in getNewOpcode()
1766 return AMDGPU::GLOBAL_LOAD_DWORDX3_SADDR; in getNewOpcode()
1768 return AMDGPU::GLOBAL_LOAD_DWORDX4_SADDR; in getNewOpcode()
1775 return AMDGPU::GLOBAL_STORE_DWORDX2; in getNewOpcode()
1777 return AMDGPU::GLOBAL_STORE_DWORDX3; in getNewOpcode()
1779 return AMDGPU::GLOBAL_STORE_DWORDX4; in getNewOpcode()
1786 return AMDGPU::GLOBAL_STORE_DWORDX2_SADDR; in getNewOpcode()
1788 return AMDGPU::GLOBAL_STORE_DWORDX3_SADDR; in getNewOpcode()
1790 return AMDGPU::GLOBAL_STORE_DWORDX4_SADDR; in getNewOpcode()
1797 return AMDGPU::FLAT_LOAD_DWORDX2; in getNewOpcode()
1799 return AMDGPU::FLAT_LOAD_DWORDX3; in getNewOpcode()
1801 return AMDGPU::FLAT_LOAD_DWORDX4; in getNewOpcode()
1808 return AMDGPU::FLAT_STORE_DWORDX2; in getNewOpcode()
1810 return AMDGPU::FLAT_STORE_DWORDX3; in getNewOpcode()
1812 return AMDGPU::FLAT_STORE_DWORDX4; in getNewOpcode()
1817 return AMDGPU::getMaskedMIMGOp(CI.I->getOpcode(), Width); in getNewOpcode()
1833 {AMDGPU::sub0, AMDGPU::sub0_sub1, AMDGPU::sub0_sub1_sub2, AMDGPU::sub0_sub1_sub2_sub3}, in getSubRegIdxs()
1834 {AMDGPU::sub1, AMDGPU::sub1_sub2, AMDGPU::sub1_sub2_sub3, AMDGPU::sub1_sub2_sub3_sub4}, in getSubRegIdxs()
1835 {AMDGPU::sub2, AMDGPU::sub2_sub3, AMDGPU::sub2_sub3_sub4, AMDGPU::sub2_sub3_sub4_sub5}, in getSubRegIdxs()
1836 {AMDGPU::sub3, AMDGPU::sub3_sub4, AMDGPU::sub3_sub4_sub5, AMDGPU::sub3_sub4_sub5_sub6}, in getSubRegIdxs()
1837 {AMDGPU::sub4, AMDGPU::sub4_sub5, AMDGPU::sub4_sub5_sub6, AMDGPU::sub4_sub5_sub6_sub7}, in getSubRegIdxs()
1863 return &AMDGPU::SReg_64_XEXECRegClass; in getTargetRegisterClass()
1865 return &AMDGPU::SGPR_96RegClass; in getTargetRegisterClass()
1867 return &AMDGPU::SGPR_128RegClass; in getTargetRegisterClass()
1869 return &AMDGPU::SGPR_256RegClass; in getTargetRegisterClass()
1871 return &AMDGPU::SGPR_512RegClass; in getTargetRegisterClass()
1890 copyFromSrcRegs(CI, Paired, InsertBefore, AMDGPU::OpName::vdata); in mergeBufferStorePair()
1898 MIB.add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::vaddr)); in mergeBufferStorePair()
1907 MIB.add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::srsrc)) in mergeBufferStorePair()
1908 .add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::soffset)) in mergeBufferStorePair()
1925 Register Reg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass); in createRegOrImm()
1928 TII->get(AMDGPU::S_MOV_B32), Reg) in createRegOrImm()
1955 const auto *CarryRC = TRI->getRegClass(AMDGPU::SReg_1_XEXECRegClassID); in computeBase()
1959 Register DestSub0 = MRI->createVirtualRegister(&AMDGPU::VGPR_32RegClass); in computeBase()
1960 Register DestSub1 = MRI->createVirtualRegister(&AMDGPU::VGPR_32RegClass); in computeBase()
1962 BuildMI(*MBB, MBBI, DL, TII->get(AMDGPU::V_ADD_CO_U32_e64), DestSub0) in computeBase()
1971 BuildMI(*MBB, MBBI, DL, TII->get(AMDGPU::V_ADDC_U32_e64), DestSub1) in computeBase()
1984 .addImm(AMDGPU::sub0) in computeBase()
1986 .addImm(AMDGPU::sub1); in computeBase()
1997 auto Base = TII->getNamedOperand(MI, AMDGPU::OpName::vaddr); in updateBaseAndOffset()
2000 TII->getNamedOperand(MI, AMDGPU::OpName::offset)->setImm(NewOffset); in updateBaseAndOffset()
2012 if (!Def || Def->getOpcode() != AMDGPU::S_MOV_B32 || in extractConstOffset()
2035 if (!Def || Def->getOpcode() != AMDGPU::REG_SEQUENCE in processBaseWithConstOffset()
2047 if (!BaseLoDef || BaseLoDef->getOpcode() != AMDGPU::V_ADD_CO_U32_e64 || in processBaseWithConstOffset()
2048 !BaseHiDef || BaseHiDef->getOpcode() != AMDGPU::V_ADDC_U32_e64) in processBaseWithConstOffset()
2051 const auto *Src0 = TII->getNamedOperand(*BaseLoDef, AMDGPU::OpName::src0); in processBaseWithConstOffset()
2052 const auto *Src1 = TII->getNamedOperand(*BaseLoDef, AMDGPU::OpName::src1); in processBaseWithConstOffset()
2063 Src0 = TII->getNamedOperand(*BaseHiDef, AMDGPU::OpName::src0); in processBaseWithConstOffset()
2064 Src1 = TII->getNamedOperand(*BaseHiDef, AMDGPU::OpName::src1); in processBaseWithConstOffset()
2102 if (TII->getNamedOperand(MI, AMDGPU::OpName::offset)->getImm()) { in promoteConstantOffsetToImm()
2108 MachineOperand &Base = *TII->getNamedOperand(MI, AMDGPU::OpName::vaddr); in promoteConstantOffsetToImm()
2167 TII->getNamedOperand(MINext, AMDGPU::OpName::offset)->getImm()) in promoteConstantOffsetToImm()
2171 *TII->getNamedOperand(MINext, AMDGPU::OpName::vaddr); in promoteConstantOffsetToImm()
2280 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::swz); in collectMergeableInsts()