Lines Matching refs:TII
30 const SIInstrInfo *TII = nullptr; member in __anon03252fca0111::SILateBranchLowering
81 const SIInstrInfo *TII, MachineFunction &MF) { in generateEndPgm() argument
91 bool MustExport = !AMDGPU::isGFX10Plus(TII->getSubtarget()); in generateEndPgm()
100 BuildMI(MBB, I, DL, TII->get(AMDGPU::EXP_DONE)) in generateEndPgm()
112 BuildMI(MBB, I, DL, TII->get(AMDGPU::S_ENDPGM)).addImm(0); in generateEndPgm()
156 BuildMI(*MI.getParent(), MI, DL, TII->get(AMDGPU::S_ALLOC_VGPR)); in expandChainCall()
158 *TII->getNamedOperand(MI, AMDGPU::OpName::numvgprs)); in expandChainCall()
161 BuildMI(*MI.getParent(), MI, DL, TII->get(AMDGPU::S_CSELECT_B64)) in expandChainCall()
162 .addDef(TII->getNamedOperand(MI, AMDGPU::OpName::src0)->getReg()); in expandChainCall()
164 *TII->getNamedOperand(MI, AMDGPU::OpName::src0)); in expandChainCall()
166 *TII->getNamedOperand(MI, AMDGPU::OpName::fbcallee)); in expandChainCall()
169 TII->get(ST.isWave32() ? AMDGPU::S_CSELECT_B32 in expandChainCall()
174 *TII->getNamedOperand(MI, AMDGPU::OpName::exec)); in expandChainCall()
176 *TII->getNamedOperand(MI, AMDGPU::OpName::fbexec)); in expandChainCall()
178 auto SetExec = BuildMI(*MI.getParent(), MI, DL, TII->get(MovOpc), ExecReg); in expandChainCall()
180 *TII->getNamedOperand(MI, AMDGPU::OpName::exec)); in expandChainCall()
186 MI.setDesc(TII->get(AMDGPU::SI_TCRETURN)); in expandChainCall()
194 auto BranchMI = BuildMI(MBB, MI, DL, TII->get(AMDGPU::S_CBRANCH_SCC0)) in earlyTerm()
218 TII = ST.getInstrInfo(); in run()
219 TRI = &TII->getRegisterInfo(); in run()
272 BuildMI(*EarlyExitBlock, EarlyExitBlock->end(), DL, TII->get(MovOpc), in run()
275 generateEndPgm(*EarlyExitBlock, EarlyExitBlock->end(), DL, TII, MF); in run()
314 BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(AMDGPU::S_BRANCH)) in run()