Lines Matching full:src0
69 let DisableEncoding = "$src0", Constraints = "$src0 = $vdst" in {
74 (ins VGPR_32:$src0, VGPR_32:$vsrc, InterpAttr:$attr,
77 [(set f32:$vdst, (int_amdgcn_interp_p2 f32:$src0, f32:$vsrc,
80 } // End DisableEncoding = "$src0", Constraints = "$src0 = $vdst"
124 (ins VSrc_b64:$src0, VSrc_b64:$src1, SSrc_b64:$src2), "", []> {
133 (ins VSrc_b64:$src0)> {
150 (ins i64imm:$src0)> {
162 def WQM : PseudoInstSI <(outs unknown:$vdst), (ins unknown:$src0)>;
166 def SOFT_WQM : PseudoInstSI <(outs unknown:$vdst), (ins unknown:$src0)>;
170 // the instruction that defines $src0 (which is run in Whole Wave Mode) doesn't
173 def STRICT_WWM : PseudoInstSI <(outs unknown:$vdst), (ins unknown:$src0)>;
174 def STRICT_WQM : PseudoInstSI <(outs unknown:$vdst), (ins unknown:$src0)>;
186 def ENTER_STRICT_WWM : SPseudoInstSI <(outs SReg_1:$sdst), (ins i64imm:$src0)> {
194 def EXIT_STRICT_WWM : SPseudoInstSI <(outs SReg_1:$sdst), (ins SReg_1:$src0)> {
200 def ENTER_STRICT_WQM : SPseudoInstSI <(outs SReg_1:$sdst), (ins i64imm:$src0)> {
208 def EXIT_STRICT_WQM : SPseudoInstSI <(outs SReg_1:$sdst), (ins SReg_1:$src0)> {
236 (ins VGPR_32:$src0),
237 [(set f16:$vdst, (SIfptrunc_round_upward f32:$src0))]>;
240 (ins VGPR_32:$src0),
241 [(set f16:$vdst, (SIfptrunc_round_downward f32:$src0))]>;
284 (outs VReg_64:$vdst), (ins VSrc_b64:$src0, VSrc_b64:$src1),
285 [(set VReg_64:$vdst, (DivergentBinFrag<add> i64:$src0, i64:$src1))]
289 (outs VReg_64:$vdst), (ins VSrc_b64:$src0, VSrc_b64:$src1),
290 [(set VReg_64:$vdst, (DivergentBinFrag<sub> i64:$src0, i64:$src1))]
296 (outs SReg_64:$sdst), (ins SSrc_b64:$src0, SSrc_b64:$src1),
297 [(set SReg_64:$sdst, (UniformBinFrag<add> i64:$src0, i64:$src1))]
301 (outs SReg_64:$sdst), (ins SSrc_b64:$src0, SSrc_b64:$src1),
302 [(set SReg_64:$sdst, (UniformBinFrag<sub> i64:$src0, i64:$src1))]
306 (outs SReg_32:$sdst, SSrc_i1:$scc_out), (ins SSrc_b32:$src0, SSrc_b32:$src1, SSrc_i1:$scc_in)
310 (outs SReg_32:$sdst, SSrc_i1:$scc_out), (ins SSrc_b32:$src0, SSrc_b32:$src1, SSrc_i1:$scc_in)
314 (outs SReg_32:$sdst, SSrc_i1:$scc_out), (ins SSrc_b32:$src0, SSrc_b32:$src1)
318 (outs SReg_32:$sdst, SSrc_i1:$scc_out), (ins SSrc_b32:$src0, SSrc_b32:$src1)
526 defm SI_KILL_F32_COND_IMM : PseudoInstKill <(ins VSrc_b32:$src0, i32imm:$src1, i32imm:$cond)>;
624 (outs), (ins SSrc_b64:$src0, unknown:$callee),
625 [(AMDGPUcall i64:$src0, tglobaladdr:$callee)]> {
635 (AMDGPUcall i64:$src0, (i64 0)),
636 (SI_CALL_ISEL $src0, (i64 0))
642 (outs SReg_64:$dst), (ins SSrc_b64:$src0, unknown:$callee)> {
653 (ins rc:$src0, unknown:$callee, i32imm:$fpdiff),
654 [(sd i64:$src0, tglobaladdr:$callee, i32:$fpdiff)]> {
673 (AMDGPUtc_return i64:$src0, (i64 0), (i32 timm:$fpdiff)),
674 (SI_TCRETURN CCR_SGPR_64:$src0, (i64 0), i32imm:$fpdiff)
679 (AMDGPUtc_return_gfx i64:$src0, (i64 0), (i32 timm:$fpdiff)),
680 (SI_TCRETURN_GFX Gfx_CCR_SGPR_64:$src0, (i64 0), i32imm:$fpdiff)
690 (ins CCR_SGPR_64:$src0, unknown:$callee, i32imm:$fpdiff, execrc:$exec)> {
710 (AMDGPUtc_return_chain i64:$src0, callee, (i32 timm:$fpdiff), execvt:$exec),
711 (tc CCR_SGPR_64:$src0, callee, i32imm:$fpdiff, execrc:$exec)
939 (ins SReg_32:$src0, i32imm:$src1, VGPR_32:$vdst_in)> {
950 (ins VGPR_32:$src0, i32imm:$src1)> {
1110 (f32 (any_f16_to_fp i32:$src0)),
1111 (cvt_f32_f16_inst_e64 SRCMODS.NONE, $src0)
1115 (f32 (f16_to_fp (and_oneuse i32:$src0, 0x7fff))),
1116 (cvt_f32_f16_inst_e64 SRCMODS.ABS, $src0)
1120 (f32 (f16_to_fp (i32 (srl_oneuse (and_oneuse i32:$src0, 0x7fff0000), (i32 16))))),
1121 (cvt_f32_f16_inst_e64 SRCMODS.ABS, (i32 (V_LSHRREV_B32_e64 (i32 16), i32:$src0)))
1125 (f32 (f16_to_fp (or_oneuse i32:$src0, 0x8000))),
1126 (cvt_f32_f16_inst_e64 SRCMODS.NEG_ABS, $src0)
1130 (f32 (f16_to_fp (xor_oneuse i32:$src0, 0x8000))),
1131 (cvt_f32_f16_inst_e64 SRCMODS.NEG, $src0)
1141 (i32 (AMDGPUfp_to_f16 (f32 (VOP3Mods f32:$src0, i32:$src0_modifiers)))),
1142 (cvt_f16_f32_inst_e64 $src0_modifiers, f32:$src0)
1168 (i32 (strict_fp_to_f16 (f32 (VOP3Mods f32:$src0, i32:$src0_modifiers)))),
1169 (cvt_f16_f32_inst_e64 $src0_modifiers, f32:$src0)
1186 : GCNPat <(vt (any_fmad (vt (VOP3NoMods vt:$src0)),
1189 (inst SRCMODS.NONE, $src0, SRCMODS.NONE, $src1,
1203 (f32 (fadd (AMDGPUfmul_legacy (VOP3NoMods f32:$src0),
1206 (V_MAC_LEGACY_F32_e64 SRCMODS.NONE, $src0, SRCMODS.NONE, $src1,
1214 (f32 (int_amdgcn_fma_legacy (VOP3NoMods f32:$src0),
1217 (V_FMAC_LEGACY_F32_e64 SRCMODS.NONE, $src0, SRCMODS.NONE, $src1,
1227 (f32 (fadd (AMDGPUfmul_legacy (VOP3Mods f32:$src0, i32:$src0_mod),
1230 (V_MAD_LEGACY_F32_e64 $src0_mod, $src0, $src1_mod, $src1,
1235 (vt (select i1:$src0, (VOP3ModsNonCanonicalizing vt:$src1, i32:$src1_mods),
1238 FP32InputMods:$src1_mods, VSrc_b32:$src1, SSrc_i1:$src0)
1242 (vt (select i1:$src0, vt:$src1, vt:$src2)),
1243 (V_CNDMASK_B32_e64 0, VSrc_b32:$src2, 0, VSrc_b32:$src1, SSrc_i1:$src0)
1863 (vt (AMDGPUclamp (VOP3Mods vt:$src0, i32:$src0_modifiers))),
1864 (inst i32:$src0_modifiers, vt:$src0,
1865 i32:$src0_modifiers, vt:$src0, DSTCLAMP.ENABLE, DSTOMOD.NONE)
1882 (v2f16 (AMDGPUclamp (VOP3PMods v2f16:$src0, i32:$src0_modifiers))),
1883 (V_PK_MAX_F16 $src0_modifiers, $src0,
1884 $src0_modifiers, $src0, DSTCLAMP.ENABLE)
2106 (fcopysign fp16vt:$src0, fp16vt:$src1),
2107 (V_BFI_B32_e64 (S_MOV_B32 (i32 0x00007fff)), $src0, $src1)
2111 (fcopysign f32:$src0, fp16vt:$src1),
2112 (V_BFI_B32_e64 (S_MOV_B32 (i32 0x7fffffff)), $src0,
2117 (fcopysign f64:$src0, fp16vt:$src1),
2119 (i32 (EXTRACT_SUBREG $src0, sub0)), sub0,
2120 (V_BFI_B32_e64 (S_MOV_B32 (i32 0x7fffffff)), (i32 (EXTRACT_SUBREG $src0, sub1)),
2125 (fcopysign fp16vt:$src0, f32:$src1),
2126 (V_BFI_B32_e64 (S_MOV_B32 (i32 0x00007fff)), $src0,
2131 (fcopysign fp16vt:$src0, f64:$src1),
2132 (V_BFI_B32_e64 (S_MOV_B32 (i32 0x00007fff)), $src0,
2259 (f32 (fpow (VOP3Mods f32:$src0, i32:$src0_mods), (VOP3Mods f32:$src1, i32:$src1_mods))),
2260 …E, (V_MUL_LEGACY_F32_e64 $src1_mods, $src1, SRCMODS.NONE, (V_LOG_F32_e64 $src0_mods, $src0), 0, 0))
2264 (i32 (sext i1:$src0)),
2265 (V_CNDMASK_B32_e64 /*src0mod*/(i32 0), /*src0*/(i32 0),
2266 /*src1mod*/(i32 0), /*src1*/(i32 -1), i1:$src0)
2270 (i32 (ext i1:$src0)),
2271 (V_CNDMASK_B32_e64 /*src0mod*/(i32 0), /*src0*/(i32 0),
2272 /*src1mod*/(i32 0), /*src1*/(i32 1), i1:$src0)
2281 (AMDGPUurecip i32:$src0),
2284 (V_RCP_IFLAG_F32_e32 (V_CVT_F32_U32_e32 $src0))))
2357 (fcopysign f32:$src0, f32:$src1),
2358 (V_BFI_B32_e64 (S_MOV_B32 (i32 0x7fffffff)), $src0, $src1)
2362 (fcopysign f32:$src0, f64:$src1),
2363 (V_BFI_B32_e64 (S_MOV_B32 (i32 0x7fffffff)), $src0,
2368 (fcopysign f64:$src0, f64:$src1),
2370 (i32 (EXTRACT_SUBREG $src0, sub0)), sub0,
2372 (i32 (EXTRACT_SUBREG SReg_64:$src0, sub1)),
2377 (fcopysign f64:$src0, f32:$src1),
2379 (i32 (EXTRACT_SUBREG $src0, sub0)), sub0,
2381 (i32 (EXTRACT_SUBREG SReg_64:$src0, sub1)),
2387 def : GCNPat<(i32 (trunc (srl i64:$src0, (and i32:$src1, (i32 31))))),
2388 (V_ALIGNBIT_B32_e64 (i32 (EXTRACT_SUBREG (i64 $src0), sub1)),
2389 (i32 (EXTRACT_SUBREG (i64 $src0), sub0)), $src1)>;
2391 def : GCNPat<(i32 (trunc (srl i64:$src0, (i32 ShiftAmt32Imm:$src1)))),
2392 (V_ALIGNBIT_B32_e64 (i32 (EXTRACT_SUBREG (i64 $src0), sub1)),
2393 (i32 (EXTRACT_SUBREG (i64 $src0), sub0)), $src1)>;
2438 (add (sub_oneuse (umax i32:$src0, i32:$src1),
2439 (umin i32:$src0, i32:$src1)),
2441 (V_SAD_U32_e64 $src0, $src1, $src2, (i1 0))
2445 (add (select_oneuse (i1 (setugt i32:$src0, i32:$src1)),
2446 (sub i32:$src0, i32:$src1),
2447 (sub i32:$src1, i32:$src0)),
2449 (V_SAD_U32_e64 $src0, $src1, $src2, (i1 0))
2554 (V_CNDMASK_B32_e64 /*src0mod*/(i32 0), /*src0*/(i32 0),
2580 (V_CNDMASK_B32_e64 /*src0mod*/(i32 0), /*src0*/(i32 0),
2582 (V_CNDMASK_B32_e64 /*src0mod*/(i32 0), /*src0*/(i32 0),
2587 (i1 (fp_to_int (vt (VOP3Mods vt:$src0, i32:$src0_modifiers)))),
2588 (i1 (Inst 0, (kone_type KOne), $src0_modifiers, $src0, DSTCLAMP.NONE))
2615 (i1 (and i1:$src0, i1:$src1)),
2616 (S_AND_B64 $src0, $src1)
2620 (i1 (or i1:$src0, i1:$src1)),
2621 (S_OR_B64 $src0, $src1)
2625 (i1 (xor i1:$src0, i1:$src1)),
2626 (S_XOR_B64 $src0, $src1)
2630 (i1 (add i1:$src0, i1:$src1)),
2631 (S_XOR_B64 $src0, $src1)
2635 (i1 (sub i1:$src0, i1:$src1)),
2636 (S_XOR_B64 $src0, $src1)
2641 (i1 (add i1:$src0, (i1 -1))),
2642 (S_NOT_B64 $src0)
2646 (i1 (sub i1:$src0, (i1 -1))),
2647 (S_NOT_B64 $src0)
2654 (i1 (and i1:$src0, i1:$src1)),
2655 (S_AND_B32 $src0, $src1)
2659 (i1 (or i1:$src0, i1:$src1)),
2660 (S_OR_B32 $src0, $src1)
2664 (i1 (xor i1:$src0, i1:$src1)),
2665 (S_XOR_B32 $src0, $src1)
2669 (i1 (add i1:$src0, i1:$src1)),
2670 (S_XOR_B32 $src0, $src1)
2674 (i1 (sub i1:$src0, i1:$src1)),
2675 (S_XOR_B32 $src0, $src1)
2680 (i1 (add i1:$src0, (i1 -1))),
2681 (S_NOT_B32 $src0)
2685 (i1 (sub i1:$src0, (i1 -1))),
2686 (S_NOT_B32 $src0)
2692 (i32 (DivergentBinFrag<xor> i32:$src0, (i32 -1))),
2693 (V_NOT_B32_e32 $src0)
2697 (i64 (DivergentBinFrag<xor> i64:$src0, (i64 -1))),
2699 (V_NOT_B32_e32 (i32 (EXTRACT_SUBREG i64:$src0, sub0))), sub0,
2700 (V_NOT_B32_e32 (i32 (EXTRACT_SUBREG i64:$src0, sub1))), sub1
2708 V_CNDMASK_B32_e64 /*src0mod*/(i32 0), /*src0*/(i32 0),
2717 V_CNDMASK_B32_e64 /*src0mod*/(i32 0), /*src0*/(i32 0),
2726 V_CNDMASK_B32_e64 /*src0mod*/(i32 0), /*src0*/(i32 0),
2734 V_CNDMASK_B32_e64 /*src0mod*/(i32 0), /*src0*/(i32 0),
2741 (V_CNDMASK_B32_e64 /*src0mod*/(i32 0), /*src0*/(i32 0),
2748 (V_CNDMASK_B32_e64 /*src0mod*/(i32 0), /*src0*/(i32 0),
2755 (V_CVT_F64_I32_e32 (V_CNDMASK_B32_e64 /*src0mod*/(i32 0), /*src0*/(i32 0),
2762 (V_CVT_F64_U32_e32 (V_CNDMASK_B32_e64 /*src0mod*/(i32 0), /*src0*/(i32 0),
2908 // My reading of the manual suggests we should be using src0 for the
3092 (fma (f32 (VOP3NoMods f32:$src0)),
3095 (V_FMAC_F32_e64 SRCMODS.NONE, $src0, SRCMODS.NONE, $src1,
3105 (fma (f16 (VOP3NoMods f32:$src0)),
3108 (V_FMAC_F16_e64 SRCMODS.NONE, $src0, SRCMODS.NONE, $src1,
3113 (fma (f16 (VOP3NoMods f32:$src0)),
3116 (V_FMAC_F16_t16_e64 SRCMODS.NONE, $src0, SRCMODS.NONE, $src1,
3125 (fma (f64 (VOP3NoMods f64:$src0)),
3128 (V_FMAC_F64_e64 SRCMODS.NONE, $src0, SRCMODS.NONE, $src1,
3171 (vecTy (UniformBinFrag<build_vector> (Ty SReg_32:$src0), (Ty undef))),
3172 (COPY_TO_REGCLASS SReg_32:$src0, SReg_32)
3176 (vecTy (DivergentBinFrag<build_vector> (Ty VGPR_32:$src0), (Ty undef))),
3177 (COPY_TO_REGCLASS VGPR_32:$src0, VGPR_32)
3194 (v2i16 (DivergentBinFrag<build_vector> (i16 VGPR_32:$src0), (i16 VGPR_32:$src1))),
3195 …_LSHL_OR_B32_e64 $src1, (i32 16), (i32 (V_AND_B32_e64 (i32 (V_MOV_B32_e32 (i32 0xffff))), $src0))))
3201 …(v2i16 (UniformBinFrag<build_vector> (i16 SReg_32:$src0), (i16 (trunc (srl_oneuse SReg_32:$src1, (…
3202 (v2i16 (S_PACK_LH_B32_B16 SReg_32:$src0, SReg_32:$src1))
3206 (v2i16 (UniformBinFrag<build_vector> (i16 (trunc (srl_oneuse SReg_32:$src0, (i32 16)))),
3208 (S_PACK_HH_B32_B16 SReg_32:$src0, SReg_32:$src1)
3218 (vecTy (UniformBinFrag<build_vector> (Ty SReg_32:$src0), (Ty SReg_32:$src1))),
3219 (S_PACK_LL_B32_B16 SReg_32:$src0, SReg_32:$src1)
3280 (v2f16 (is_canonicalized_2<build_vector> (f16 (VOP3Mods (f16 VGPR_32:$src0), i32:$src0_mods)),
3282 (V_PACK_B32_F16_e64 $src0_mods, VGPR_32:$src0, $src1_mods, VGPR_32:$src1)
3291 (v2i16 (build_vector (i16 (trunc (srl_oneuse SReg_32:$src0, (i32 16)))), (i16 SReg_32:$src1))),
3292 (v2i16 (S_PACK_HL_B32_B16 SReg_32:$src0, SReg_32:$src1))
3297 (v2f16 (scalar_to_vector f16:$src0)),
3298 (COPY $src0)
3302 (v2i16 (scalar_to_vector i16:$src0)),
3303 (COPY $src0)
3307 (v4i16 (scalar_to_vector i16:$src0)),
3308 (INSERT_SUBREG (IMPLICIT_DEF), $src0, sub0)
3312 (v4f16 (scalar_to_vector f16:$src0)),
3313 (INSERT_SUBREG (IMPLICIT_DEF), $src0, sub0)
3379 (UniformBinFrag<add> i32:$src0, (i32 NegSubInlineConst32:$src1)),
3380 (S_SUB_I32 SReg_32:$src0, NegSubInlineConst32:$src1)
3384 (DivergentBinFrag<add> i32:$src0, (i32 NegSubInlineConst32:$src1)),
3385 (V_SUB_U32_e64 VS_32:$src0, NegSubInlineConst32:$src1)> {
3390 (DivergentBinFrag<add> i32:$src0, (i32 NegSubInlineConst32:$src1)),
3391 (V_SUB_CO_U32_e64 VS_32:$src0, NegSubInlineConst32:$src1)> {
3502 (min (max i32:$src0, i32:$src1),
3503 (max (min i32:$src0, i32:$src1), i32:$src2)),
3504 (med3Inst VSrc_b32:$src0, VSrc_b32:$src1, VSrc_b32:$src2)
3510 (max (min i32:$src0, i32:$src1),
3511 (min (max i32:$src0, i32:$src1), i32:$src2)),
3512 (med3Inst VSrc_b32:$src0, VSrc_b32:$src1, VSrc_b32:$src2)
3524 (fminnum_like (VOP3Mods vt:$src0, i32:$src0_mods),
3526 (fminnum_like (fmaxnum_like (VOP3Mods vt:$src0, i32:$src0_mods),
3529 (med3Inst $src0_mods, $src0, $src1_mods, $src1, $src2_mods, $src2,
3536 (fmaxnum_like (VOP3Mods vt:$src0, i32:$src0_mods),
3538 (fmaxnum_like (fminnum_like (VOP3Mods vt:$src0, i32:$src0_mods),
3541 (med3Inst $src0_mods, $src0, $src1_mods, $src1, $src2_mods, $src2,
3551 (max (min i16:$src0, i16:$src1),
3552 (min (max i16:$src0, i16:$src1), i16:$src2)),
3553 …(med3Inst SRCMODS.NONE, VSrc_b16:$src0, SRCMODS.NONE, VSrc_b16:$src1, SRCMODS.NONE, VSrc_b16:$src2…
3559 (min (max i16:$src0, i16:$src1),
3560 (max (min i16:$src0, i16:$src1), i16:$src2)),
3561 …(med3Inst SRCMODS.NONE, VSrc_b16:$src0, SRCMODS.NONE, VSrc_b16:$src1, SRCMODS.NONE, VSrc_b16:$src2…
3574 (DivergentBinFrag<min_or_max> (max_or_min_oneuse i32:$src0, i32:$src1),
3576 (minmaxInst VSrc_b32:$src0, VSrc_b32:$src1, VSrc_b32:$src2)
3582 (min_or_max (max_or_min_oneuse (VOP3Mods vt:$src0, i32:$src0_mods),
3585 (minmaxInst $src0_mods, $src0, $src1_mods, $src1, $src2_mods, $src2,
3593 (max_or_min_oneuse (VOP3Mods vt:$src0, i32:$src0_mods),
3596 (minmaxInst $src0_mods, $src0, $src1_mods, $src1, $src2_mods, $src2,
3677 (any_fmul (f64 (VOP3Mods f64:$src0, i32:$src0_mods)),
3679 (V_LDEXP_F64_e64 i32:$src0_mods, VSrc_b64:$src0,
3684 (any_fmul f64:$src0, fpimm_neg_pow2_prefer_ldexp_f64:$src1),
3685 (V_LDEXP_F64_e64 SRCMODS.NEG, VSrc_b64:$src0,
3694 (any_fmul (fabs f64:$src0), fpimm_neg_pow2_prefer_ldexp_f64:$src1),
3695 (V_LDEXP_F64_e64 SRCMODS.NEG_ABS, VSrc_b64:$src0,
3795 let InOperandList = (ins type0:$src0, type0:$src1);
3801 let InOperandList = (ins type0:$src0, type0:$src1);
3808 let InOperandList = (ins type0:$src0);
3815 let InOperandList = (ins type0:$src0, type0:$src1);
3821 let InOperandList = (ins type0:$src0, type0:$src1, type0:$src2);
3827 let InOperandList = (ins type0:$src0, type0:$src1, type0:$src2);
3833 let InOperandList = (ins type0:$src0, type0:$src1, type0:$src2);
3924 let InOperandList = (ins type0:$src0, type0:$src1);
3930 let InOperandList = (ins type0:$src0, type0:$src1);
3992 let InOperandList = (ins type0:$src0, unknown:$callee);
4003 let InOperandList = (ins type1:$src0);
4009 let InOperandList = (ins type1:$src0);