Lines Matching +full:abs +full:- +full:flat
1 //===-- SIInstrInfo.td -----------------------------------------------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 def isWave32 : Predicate<"Subtarget->getWavefrontSize() == 32">,
11 def isWave64 : Predicate<"Subtarget->getWavefrontSize() == 64">,
21 int NONE = -1;
36 //===----------------------------------------------------------------------===//
38 //===----------------------------------------------------------------------===//
51 //===----------------------------------------------------------------------===//
53 //===----------------------------------------------------------------------===//
315 //===----------------------------------------------------------------------===//
317 //===----------------------------------------------------------------------===//
323 //===----------------------------------------------------------------------===//
326 // enable s_mov_b32 m0, -1 to be glued to the memory instructions.
331 //===----------------------------------------------------------------------===//
520 let PredicateCode = [{return cast<MemSDNode>(N)->getAlign() < 4;}],
521 GISelPredicateCode = [{return (*MI.memoperands_begin())->getAlign() < 4;}],
588 //===----------------------------------------------------------------------===//
592 //===----------------------------------------------------------------------===//
630 //===----------------------------------------------------------------------===//
632 //===----------------------------------------------------------------------===//
640 foreach as = [ "global", "flat", "constant", "local", "private", "region" ] in {
691 foreach I = 1-4 in {
749 return CurDAG->getTargetConstant(N->getZExtValue(), SDLoc(N), MVT::i1);
753 return CurDAG->getTargetConstant(N->getZExtValue(), SDLoc(N), MVT::i8);
757 return CurDAG->getTargetConstant(N->getSExtValue(), SDLoc(N), MVT::i16);
761 return CurDAG->getTargetConstant(N->getSExtValue(), SDLoc(N), MVT::i16);
765 return CurDAG->getTargetConstant(N->getSExtValue(), SDLoc(N), MVT::i16);
769 return CurDAG->getTargetConstant(N->getSExtValue(), SDLoc(N), MVT::i32);
773 return CurDAG->getTargetConstant(N->getSExtValue(), SDLoc(N), MVT::i32);
777 return CurDAG->getTargetConstant(N->getSExtValue(), SDLoc(N), MVT::i64);
781 return CurDAG->getTargetConstant(N->get(), SDLoc(N), MVT::i32);
786 return CurDAG->getTargetConstant(
787 N->getValueAPF().bitcastToAPInt().getZExtValue(), SDLoc(N), MVT::i32);
792 return CurDAG->getTargetFrameIndex(FI->getIndex(), MVT::i32);
797 return CurDAG->getTargetConstant(
798 N->getValueAPF().bitcastToAPInt().getZExtValue(), SDLoc(N), MVT::i64);
802 uint64_t Imm = N->getZExtValue();
804 return CurDAG->getTargetConstant(Bit, SDLoc(N), MVT::i1);
834 return CurDAG->getConstant(-N->getSExtValue(), SDLoc(N), MVT::i32);
839 return Imm < -16 && Imm >= -64;
843 return Imm < -16 && Imm >= -64;
851 return fp16SrcZerosHighBits(N->getOpcode());
864 return TLI->isCanonicalized(Dst.getReg(), MF);
868 //===----------------------------------------------------------------------===//
870 //===----------------------------------------------------------------------===//
873 return CurDAG->getTargetConstant(
874 N->getZExtValue() & (Subtarget->getGeneration() >= AMDGPUSubtarget::GFX12
882 N->getZExtValue() & (Subtarget->getGeneration() >= AMDGPUSubtarget::GFX12
885 return CurDAG->getTargetConstant(Swizzle, SDLoc(N), MVT::i8);
889 const uint32_t cpol = N->getZExtValue() & (Subtarget->getGeneration() >= AMDGPUSubtarget::GFX12
892 return CurDAG->getTargetConstant(cpol | AMDGPU::CPol::GLC, SDLoc(N), MVT::i8);
895 //===----------------------------------------------------------------------===//
897 //===----------------------------------------------------------------------===//
972 // ===----------------------------------------------------------------------===//
975 // ===----------------------------------------------------------------------===//
1022 "getPredicate([](const AMDGPUOperand &Op) -> bool { "#
1027 "[this](OperandVector &Operands) -> ParseStatus { "#
1036 "[this](OperandVector &Operands) -> ParseStatus { "#
1053 "[this](OperandVector &Operands) -> ParseStatus { "#
1061 "[this](OperandVector &Operands) -> ParseStatus { "#
1130 let ConvertMethod = "[this] (int64_t &BC) -> bool { return convertDppBoundCtrl(BC); }";
1172 // 32-bit VALU immediate operand that uses the constant bus.
1175 // 32-bit VALU immediate operand with a 16-bit value that uses the
1372 //===----------------------------------------------------------------------===//
1374 //===----------------------------------------------------------------------===//
1420 //===----------------------------------------------------------------------===//
1422 //===----------------------------------------------------------------------===//
1434 int ABS = 2;
1437 int NEG_HI = ABS;
1475 !shl(!add(Size, -1), 11)), 65535);
1478 //===----------------------------------------------------------------------===//
1482 // Instructions with _32 take 32-bit operands.
1483 // Instructions with _64 take 64-bit operands.
1485 // VOP_* instructions can use either a 32-bit or 64-bit encoding. The 32-bit
1487 // any of the instruction modifiers must use the 64-bit encoding.
1489 // Instructions with _e32 use the 32-bit encoding.
1490 // Instructions with _e64 use the 64-bit encoding.
1492 //===----------------------------------------------------------------------===//
1499 //===----------------------------------------------------------------------===//
1501 //===----------------------------------------------------------------------===//
1538 VOPDstOperand<VGPR_32>); // VOP1/2 32-bit dst
1965 (outs), // no dst for VOPC, we use "vcc"-token as dst in SDWA VOPC instructions
2202 0, // NumSrcArgs == 3 - No SDWA for VOP3
2204 0, // 64-bit dst - No SDWA for 64-bit operands
2206 0, // 64-bit src0
2208 0, // 64-bit src2
2218 0, // NumSrcArgs == 3 - No DPP for VOP3
2255 0, // 64-bit dst No DPP for 64-bit operands
2257 0, // 64-bit src0
2259 0, // 64-bit src1
2261 0, // 64-bit src2
2431 // It is a slight misnomer to use the deferred f32 operand type for non-float
2491 // Most DstVT are 16-bit, but not all.
2518 // Most DstVT are 16-bit, but not all
2651 //===----------------------------------------------------------------------===//
2653 //===----------------------------------------------------------------------===//
2664 // FIXME-GFX10: WIP.
2681 // FIXME-GFX10: WIP.
2697 //===----------------------------------------------------------------------===//
2699 //===----------------------------------------------------------------------===//
2857 // Maps flat scratch opcodes by addressing modes