Lines Matching +full:ri +full:- +full:override
1 //===- SIInstrInfo.h - SI Instruction Info Interface ------------*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
85 const SIRegisterInfo RI;
94 SCC_FALSE = -1,
96 VCCZ = -2,
97 EXECNZ = -3,
186 isCopyInstrImpl(const MachineInstr &MI) const override;
194 unsigned OpIdx1) const override;
201 // MO_GOTPCREL -> symbol@GOTPCREL -> R_AMDGPU_GOTPCREL.
203 // MO_GOTPCREL32_LO -> symbol@gotpcrel32@lo -> R_AMDGPU_GOTPCREL32_LO.
206 // MO_GOTPCREL32_HI -> symbol@gotpcrel32@hi -> R_AMDGPU_GOTPCREL32_HI.
208 // MO_REL32_LO -> symbol@rel32@lo -> R_AMDGPU_REL32_LO.
211 // MO_REL32_HI -> symbol@rel32@hi -> R_AMDGPU_REL32_HI.
223 return RI; in getRegisterInfo()
230 bool isReallyTriviallyReMaterializable(const MachineInstr &MI) const override;
232 bool isIgnorableUse(const MachineOperand &MO) const override;
235 MachineCycleInfo *CI) const override;
238 int64_t &Offset1) const override;
251 unsigned NumBytes) const override;
254 int64_t Offset1, unsigned NumLoads) const override;
258 bool KillSrc) const override;
280 Register VReg) const override;
286 Register VReg) const override;
288 bool expandPostRAPseudo(MachineInstr &MI) const override;
293 const TargetRegisterInfo &TRI) const override;
297 // Can split either post-RA with physical registers or pre-RA with
323 unsigned &SrcOpIdx1) const override;
329 int64_t BrOffset) const override;
331 MachineBasicBlock *getBranchDestBlock(const MachineInstr &MI) const override;
340 int64_t BrOffset, RegScavenger *RS) const override;
352 bool AllowModify = false) const override;
355 int *BytesRemoved = nullptr) const override;
360 int *BytesAdded = nullptr) const override;
363 SmallVectorImpl<MachineOperand> &Cond) const override;
368 int &TrueCycles, int &FalseCycles) const override;
373 Register TrueReg, Register FalseReg) const override;
382 int64_t &CmpValue) const override;
386 const MachineRegisterInfo *MRI) const override;
390 const MachineInstr &MIb) const override;
399 unsigned getMachineCSELookAheadLimit() const override { return 500; } in getMachineCSELookAheadLimit()
402 LiveIntervals *LIS) const override;
406 const MachineFunction &MF) const override;
861 // Most sopk treat the immediate as a signed 16-bit, however some
1014 const MachineFunction &MF = *MI.getParent()->getParent(); in isVGPRCopy()
1016 return !RI.isSGPRReg(MRI, Dest); in isVGPRCopy()
1020 const MachineFunction &MF = *MI.getParent()->getParent(); in hasVGPRUses()
1024 return MO.isReg() && RI.isVGPR(MRI, MO.getReg());}); in hasVGPRUses()
1047 // Returns true if this non-register operand definitely does not need to be
1048 // encoded as a 32-bit literal. Note that this function handles all kinds of
1052 // that will not require an additional 4-bytes; this function assumes that it
1105 /// Return true if this 64-bit VALU instruction has a 32-bit encoding.
1106 /// This function will return false if you pass it a 32-bit instruction.
1129 StringRef &ErrInfo) const override;
1142 /// Return the correct register class for \p OpNo. For target-specific
1155 if (OpInfo.RegClass == -1) { in getOpSize()
1156 // If this is an immediate operand, this must be a 32-bit literal. in getOpSize()
1161 return RI.getRegSizeInBits(*RI.getRegClass(OpInfo.RegClass)) / 8; in getOpSize()
1170 return RI.getSubRegIdxSize(SubReg) / 8; in getOpSize()
1173 return RI.getRegSizeInBits(*getOpRegClass(MI, OpNo)) / 8; in getOpSize()
1229 /// instructions and control-flow around \p MI. If present, \p MDT is
1249 MachineBasicBlock::iterator MI) const override;
1252 unsigned Quantity) const override;
1289 bool isHighLatencyDef(int Opc) const override;
1291 /// Return the descriptor of the target-specific machine instruction
1301 int &FrameIndex) const override;
1303 int &FrameIndex) const override;
1306 unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
1319 decomposeMachineOperandsTargetFlags(unsigned TF) const override;
1322 getSerializableTargetIndices() const override;
1325 getSerializableDirectMachineOperandTargetFlags() const override;
1328 getSerializableMachineMemOperandTargetFlags() const override;
1332 const ScheduleDAG *DAG) const override;
1335 CreateTargetPostRAHazardRecognizer(const MachineFunction &MF) const override;
1339 const ScheduleDAGMI *DAG) const override;
1342 const MachineFunction &MF) const override;
1345 Register Reg = Register()) const override;
1350 Register Dst) const override;
1356 Register Dst) const override;
1362 /// For pre-GFX9 it will generate unused carry destination operand.
1363 /// TODO: After GFX9 it should return a no-carry operation.
1400 /// \brief Return a target-specific opcode if Opcode is a pseudo instruction.
1401 /// Return -1 if the target-specific opcode for the pseudo instruction does
1412 const override;
1421 VirtRegMap *VRM = nullptr) const override;
1425 unsigned *PredCost = nullptr) const override;
1428 getInstructionUniformity(const MachineInstr &MI) const override final;
1433 const MIRFormatter *getMIRFormatter() const override { in getMIRFormatter()
1457 return RC == TRI->getMatchingSuperRegClass(RC, &TRC, P.SubReg); in isOfRegClass()
1472 /// skipping copy like instructions and subreg-manipulation pseudos.
1523 /// \returns \p Opcode if it is an Addr64 opcode, otherwise -1.