Lines Matching refs:VRC
5644 const TargetRegisterClass *VRC = RI.getEquivalentVGPRClass(RC); in legalizeOpWithMove() local
5645 Register Reg = MRI.createVirtualRegister(VRC); in legalizeOpWithMove()
6059 const TargetRegisterClass *VRC = MRI.getRegClass(SrcReg); in readlaneVGPRToSGPR() local
6060 const TargetRegisterClass *SRC = RI.getEquivalentSGPRClass(VRC); in readlaneVGPRToSGPR()
6062 unsigned SubRegs = RI.getRegSizeInBits(*VRC) / 32; in readlaneVGPRToSGPR()
6064 if (RI.hasAGPRs(VRC)) { in readlaneVGPRToSGPR()
6065 VRC = RI.getEquivalentVGPRClass(VRC); in readlaneVGPRToSGPR()
6066 Register NewSrcReg = MRI.createVirtualRegister(VRC); in readlaneVGPRToSGPR()
6588 const TargetRegisterClass *RC = nullptr, *SRC = nullptr, *VRC = nullptr; in legalizeOperands() local
6595 VRC = OpRC; in legalizeOperands()
6604 if (VRC || !RI.isSGPRClass(getOpRegClass(MI, 0))) { in legalizeOperands()
6605 if (!VRC) { in legalizeOperands()
6608 VRC = &AMDGPU::VReg_1RegClass; in legalizeOperands()
6610 VRC = RI.isAGPRClass(getOpRegClass(MI, 0)) in legalizeOperands()
6614 VRC = RI.isAGPRClass(getOpRegClass(MI, 0)) in legalizeOperands()
6615 ? RI.getEquivalentAGPRClass(VRC) in legalizeOperands()
6616 : RI.getEquivalentVGPRClass(VRC); in legalizeOperands()
6618 RC = VRC; in legalizeOperands()
6655 const TargetRegisterClass *VRC = RI.getEquivalentVGPRClass(OpRC); in legalizeOperands() local
6656 if (VRC == OpRC) in legalizeOperands()
6659 legalizeGenericOperand(*MBB, MI, VRC, Op, MRI, MI.getDebugLoc()); in legalizeOperands()