63 SIInstrInfo::SIInstrInfo(const GCNSubtarget &ST)  in SIInstrInfo()  function in SIInstrInfo
109   if (SIInstrInfo::isVOP1(MI) || SIInstrInfo::isVOP2(MI) ||  in canRemat()
110       SIInstrInfo::isVOP3(MI) || SIInstrInfo::isSDWA(MI) ||  in canRemat()
111       SIInstrInfo::isSALU(MI))  in canRemat()
114   if (SIInstrInfo::isSMRD(MI)) {  in canRemat()
124 bool SIInstrInfo::isReallyTriviallyReMaterializable(  in isReallyTriviallyReMaterializable()
184 bool SIInstrInfo::isIgnorableUse(const MachineOperand &MO) const {  in isIgnorableUse()
190 bool SIInstrInfo::isSafeToSink(MachineInstr &MI,  in isSafeToSink()
230 bool SIInstrInfo::areLoadsFromSameBasePtr(SDNode *Load0, SDNode *Load1,  in areLoadsFromSameBasePtr()
356 bool SIInstrInfo::getMemOperandsWithOffsetWidth(  in getMemOperandsWithOffsetWidth()
549 bool SIInstrInfo::shouldClusterMemOps(ArrayRef<const MachineOperand *> BaseOps1,  in shouldClusterMemOps()
594 bool SIInstrInfo::shouldScheduleLoadsNear(SDNode *Load0, SDNode *Load1,  in shouldScheduleLoadsNear()
606 static void reportIllegalCopy(const SIInstrInfo *TII, MachineBasicBlock &MBB,  in reportIllegalCopy()
623 static void indirectCopyToAGPR(const SIInstrInfo &TII,  in indirectCopyToAGPR()
742 static void expandSGPRCopy(const SIInstrInfo &TII, MachineBasicBlock &MBB,  in expandSGPRCopy()
794 void SIInstrInfo::copyPhysReg(MachineBasicBlock &MBB,  in copyPhysReg()
1147 int SIInstrInfo::commuteOpcode(unsigned Opcode) const {  in commuteOpcode()
1165 void SIInstrInfo::materializeImmediate(MachineBasicBlock &MBB,  in materializeImmediate()
1222 SIInstrInfo::getPreferredSelectRegClass(unsigned Size) const {  in getPreferredSelectRegClass()
1226 void SIInstrInfo::insertVectorSelect(MachineBasicBlock &MBB,  in insertVectorSelect()
1251     case SIInstrInfo::SCC_TRUE: {  in insertVectorSelect()
1265     case SIInstrInfo::SCC_FALSE: {  in insertVectorSelect()
1279     case SIInstrInfo::VCCNZ: {  in insertVectorSelect()
1293     case SIInstrInfo::VCCZ: {  in insertVectorSelect()
1307     case SIInstrInfo::EXECNZ: {  in insertVectorSelect()
1325     case SIInstrInfo::EXECZ: {  in insertVectorSelect()
1352 Register SIInstrInfo::insertEQ(MachineBasicBlock *MBB,  in insertEQ()
1365 Register SIInstrInfo::insertNE(MachineBasicBlock *MBB,  in insertNE()
1378 unsigned SIInstrInfo::getMovOpcode(const TargetRegisterClass *DstRC) const {  in getMovOpcode()
1397 SIInstrInfo::getIndirectGPRIDXPseudo(unsigned VecSize,  in getIndirectGPRIDXPseudo()
1530 SIInstrInfo::getIndirectRegWriteMovRelPseudo(unsigned VecSize, unsigned EltSize,  in getIndirectRegWriteMovRelPseudo()
1717 void SIInstrInfo::storeRegToStackSlot(  in storeRegToStackSlot()
1942 void SIInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,  in loadRegFromStackSlot()
1994 void SIInstrInfo::insertNoop(MachineBasicBlock &MBB,  in insertNoop()
1999 void SIInstrInfo::insertNoops(MachineBasicBlock &MBB,  in insertNoops()
2010 void SIInstrInfo::insertReturn(MachineBasicBlock &MBB) const {  in insertReturn()
2028 MachineBasicBlock *SIInstrInfo::insertSimulatedTrap(MachineRegisterInfo &MRI,  in insertSimulatedTrap()
2086 unsigned SIInstrInfo::getNumWaitStates(const MachineInstr &MI) {  in getNumWaitStates()
2100 bool SIInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {  in expandPostRAPseudo()
2560 void SIInstrInfo::reMaterialize(MachineBasicBlock &MBB,  in reMaterialize()
2647 SIInstrInfo::expandMovDPP64(MachineInstr &MI) const {  in expandMovDPP64()
2711 SIInstrInfo::isCopyInstrImpl(const MachineInstr &MI) const {  in isCopyInstrImpl()
2718 bool SIInstrInfo::swapSourceModifiers(MachineInstr &MI,  in swapSourceModifiers()
2768 MachineInstr *SIInstrInfo::commuteInstructionImpl(MachineInstr &MI, bool NewMI,  in commuteInstructionImpl()
2823 bool SIInstrInfo::findCommutedOpIndices(const MachineInstr &MI,  in findCommutedOpIndices()
2829 bool SIInstrInfo::findCommutedOpIndices(const MCInstrDesc &Desc,  in findCommutedOpIndices()
2847 bool SIInstrInfo::isBranchOffsetInRange(unsigned BranchOp,  in isBranchOffsetInRange()
2864 SIInstrInfo::getBranchDestBlock(const MachineInstr &MI) const {  in getBranchDestBlock()
2868 bool SIInstrInfo::hasDivergentBranch(const MachineBasicBlock *MBB) const {  in hasDivergentBranch()
2878 void SIInstrInfo::insertIndirectBranch(MachineBasicBlock &MBB,  in insertIndirectBranch()
2996 unsigned SIInstrInfo::getBranchOpcode(SIInstrInfo::BranchPredicate Cond) {  in getBranchOpcode()
2998   case SIInstrInfo::SCC_TRUE:  in getBranchOpcode()
3000   case SIInstrInfo::SCC_FALSE:  in getBranchOpcode()
3002   case SIInstrInfo::VCCNZ:  in getBranchOpcode()
3004   case SIInstrInfo::VCCZ:  in getBranchOpcode()
3006   case SIInstrInfo::EXECNZ:  in getBranchOpcode()
3008   case SIInstrInfo::EXECZ:  in getBranchOpcode()
3015 SIInstrInfo::BranchPredicate SIInstrInfo::getBranchPredicate(unsigned Opcode) {  in getBranchPredicate()
3034 bool SIInstrInfo::analyzeBranchImpl(MachineBasicBlock &MBB,  in analyzeBranchImpl()
3077 bool SIInstrInfo::analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,  in analyzeBranch()
3122 unsigned SIInstrInfo::removeBranch(MachineBasicBlock &MBB,  in removeBranch()
3148 unsigned SIInstrInfo::insertBranch(MachineBasicBlock &MBB,  in insertBranch()
3207 bool SIInstrInfo::reverseBranchCondition(  in reverseBranchCondition()
3221 bool SIInstrInfo::canInsertSelect(const MachineBasicBlock &MBB,  in canInsertSelect()
3263 void SIInstrInfo::insertSelect(MachineBasicBlock &MBB,  in insertSelect()
3370 bool SIInstrInfo::isFoldableCopy(const MachineInstr &MI) {  in isFoldableCopy()
3396 void SIInstrInfo::removeModOperands(MachineInstr &MI) const {  in removeModOperands()
3405 bool SIInstrInfo::foldImmediate(MachineInstr &UseMI, MachineInstr &DefMI,  in foldImmediate()
3698 bool SIInstrInfo::checkInstOffsetsDoNotOverlap(const MachineInstr &MIa,  in checkInstOffsetsDoNotOverlap()
3722 bool SIInstrInfo::areMemAccessesTriviallyDisjoint(const MachineInstr &MIa,  in areMemAccessesTriviallyDisjoint()
3791   if (Def && SIInstrInfo::isFoldableCopy(*Def) && Def->getOperand(1).isImm()) {  in getFoldableImm()
3821 MachineInstr *SIInstrInfo::convertToThreeAddress(MachineInstr &MI,  in convertToThreeAddress()
3860   if (SIInstrInfo::isWMMA(MI)) {  in convertToThreeAddress()
4077 bool SIInstrInfo::isSchedulingBoundary(const MachineInstr &MI,  in isSchedulingBoundary()
4108 bool SIInstrInfo::isAlwaysGDS(uint16_t Opcode) const {  in isAlwaysGDS()
4112 bool SIInstrInfo::modifiesModeRegister(const MachineInstr &MI) {  in modifiesModeRegister()
4119 bool SIInstrInfo::hasUnwantedEffectsWhenEXECEmpty(const MachineInstr &MI) const {  in hasUnwantedEffectsWhenEXECEmpty()
4165 bool SIInstrInfo::mayReadEXEC(const MachineRegisterInfo &MRI,  in mayReadEXEC()
4190 bool SIInstrInfo::isInlineConstant(const APInt &Imm) const {  in isInlineConstant()
4210 bool SIInstrInfo::isInlineConstant(const APFloat &Imm) const {  in isInlineConstant()
4229 bool SIInstrInfo::isInlineConstant(const MachineOperand &MO,  in isInlineConstant()
4355 bool SIInstrInfo::isImmOperandLegal(const MachineInstr &MI, unsigned OpNo,  in isImmOperandLegal()
4385 bool SIInstrInfo::hasVALU32BitEncoding(unsigned Opcode) const {  in hasVALU32BitEncoding()
4397 bool SIInstrInfo::hasModifiers(unsigned Opcode) const {  in hasModifiers()
4404 bool SIInstrInfo::hasModifiersSet(const MachineInstr &MI,  in hasModifiersSet()
4410 bool SIInstrInfo::hasAnyModifiersSet(const MachineInstr &MI) const {  in hasAnyModifiersSet()
4415 bool SIInstrInfo::canShrink(const MachineInstr &MI,  in canShrink()
4486 MachineInstr *SIInstrInfo::buildShrunkInst(MachineInstr &MI,  in buildShrunkInst()
4532 bool SIInstrInfo::usesConstantBus(const MachineRegisterInfo &MRI,  in usesConstantBus()
4581   if (SIInstrInfo::isVALU(MI)) {  in shouldReadExec()
4594       SIInstrInfo::isGenericOpcode(MI.getOpcode()) ||  in shouldReadExec()
4595       SIInstrInfo::isSALU(MI) ||  in shouldReadExec()
4596       SIInstrInfo::isSMRD(MI))  in shouldReadExec()
4612 bool SIInstrInfo::verifyInstruction(const MachineInstr &MI,  in verifyInstruction()
4615   if (SIInstrInfo::isGenericOpcode(MI.getOpcode()))  in verifyInstruction()
5341 unsigned SIInstrInfo::getVALUOp(const MachineInstr &MI) const {  in getVALUOp()
5502 void SIInstrInfo::insertScratchExecCopy(MachineFunction &MF,  in insertScratchExecCopy()
5509   const SIInstrInfo *TII = ST.getInstrInfo();  in insertScratchExecCopy()
5535 void SIInstrInfo::restoreExec(MachineFunction &MF, MachineBasicBlock &MBB,  in restoreExec()
5583 const TargetRegisterClass *SIInstrInfo::getRegClass(const MCInstrDesc &TID,  in getRegClass()
5613 const TargetRegisterClass *SIInstrInfo::getOpRegClass(const MachineInstr &MI,  in getOpRegClass()
5630 void SIInstrInfo::legalizeOpWithMove(MachineInstr &MI, unsigned OpIdx) const {  in legalizeOpWithMove()
5651 unsigned SIInstrInfo::buildExtractSubReg(  in buildExtractSubReg()
5665 MachineOperand SIInstrInfo::buildExtractSubRegOrImm(  in buildExtractSubRegOrImm()
5684 void SIInstrInfo::swapOperands(MachineInstr &Inst) const {  in swapOperands()
5691 bool SIInstrInfo::isLegalRegOperand(const MachineRegisterInfo &MRI,  in isLegalRegOperand()
5718 bool SIInstrInfo::isLegalVSrcOperand(const MachineRegisterInfo &MRI,  in isLegalVSrcOperand()
5729 bool SIInstrInfo::isOperandLegal(const MachineInstr &MI, unsigned OpIdx,  in isOperandLegal()
5848 void SIInstrInfo::legalizeOperandsVOP2(MachineRegisterInfo &MRI,  in legalizeOperandsVOP2()
5966 void SIInstrInfo::legalizeOperandsVOP3(MachineRegisterInfo &MRI,  in legalizeOperandsVOP3()
6057 Register SIInstrInfo::readlaneVGPRToSGPR(Register SrcReg, MachineInstr &UseMI,  in readlaneVGPRToSGPR()
6099 void SIInstrInfo::legalizeOperandsSMRD(MachineRegisterInfo &MRI,  in legalizeOperandsSMRD()
6118 bool SIInstrInfo::moveFlatAddrToVGPR(MachineInstr &Inst) const {  in moveFlatAddrToVGPR()
6199 void SIInstrInfo::legalizeOperandsFLAT(MachineRegisterInfo &MRI,  in legalizeOperandsFLAT()
6217 void SIInstrInfo::legalizeGenericOperand(MachineBasicBlock &InsertMBB,  in legalizeGenericOperand()
6263     const SIInstrInfo &TII, MachineRegisterInfo &MRI, MachineBasicBlock &OrigBB,  in emitLoadScalarOpsFromVGPRLoop()
6405 loadMBUFScalarOperandsFromVGPR(const SIInstrInfo &TII, MachineInstr &MI,  in loadMBUFScalarOperandsFromVGPR()
6512 extractRsrcPtr(const SIInstrInfo &TII, MachineInstr &MI, MachineOperand &Rsrc) {  in extractRsrcPtr()
6554 SIInstrInfo::legalizeOperands(MachineInstr &MI,  in legalizeOperands()
6951 void SIInstrInfo::moveToVALU(SIInstrWorklist &Worklist,  in moveToVALU()
6972 void SIInstrInfo::moveToVALUImpl(SIInstrWorklist &Worklist,  in moveToVALUImpl()
7507 SIInstrInfo::moveScalarAddSub(SIInstrWorklist &Worklist, MachineInstr &Inst,  in moveScalarAddSub()
7542 void SIInstrInfo::lowerSelect(SIInstrWorklist &Worklist, MachineInstr &Inst,  in lowerSelect()
7625 void SIInstrInfo::lowerScalarAbs(SIInstrWorklist &Worklist,  in lowerScalarAbs()
7652 void SIInstrInfo::lowerScalarXnor(SIInstrWorklist &Worklist,  in lowerScalarXnor()
7717 void SIInstrInfo::splitScalarNotBinop(SIInstrWorklist &Worklist,  in splitScalarNotBinop()
7746 void SIInstrInfo::splitScalarBinOpN2(SIInstrWorklist &Worklist,  in splitScalarBinOpN2()
7775 void SIInstrInfo::splitScalar64BitUnaryOp(SIInstrWorklist &Worklist,  in splitScalar64BitUnaryOp()
7836 void SIInstrInfo::splitScalarSMulU64(SIInstrWorklist &Worklist,  in splitScalarSMulU64()
7945 void SIInstrInfo::splitScalarSMulPseudo(SIInstrWorklist &Worklist,  in splitScalarSMulPseudo()
8008 void SIInstrInfo::splitScalar64BitBinaryOp(SIInstrWorklist &Worklist,  in splitScalar64BitBinaryOp()
8075 void SIInstrInfo::splitScalar64BitXnor(SIInstrWorklist &Worklist,  in splitScalar64BitXnor()
8117 void SIInstrInfo::splitScalar64BitBCNT(SIInstrWorklist &Worklist,  in splitScalar64BitBCNT()
8155 void SIInstrInfo::splitScalar64BitBFE(SIInstrWorklist &Worklist,  in splitScalar64BitBFE()
8216 void SIInstrInfo::splitScalar64BitCountOp(SIInstrWorklist &Worklist,  in splitScalar64BitCountOp()
8271 void SIInstrInfo::addUsersToMoveToVALUWorklist(  in addUsersToMoveToVALUWorklist()
8307 void SIInstrInfo::movePackToVALU(SIInstrWorklist &Worklist,  in movePackToVALU()
8380 void SIInstrInfo::addSCCDefUsersToVALUWorklist(MachineOperand &Op,  in addSCCDefUsersToVALUWorklist()
8424 void SIInstrInfo::addSCCDefsToVALUWorklist(MachineInstr *SCCUseInst,  in addSCCDefsToVALUWorklist()
8442 const TargetRegisterClass *SIInstrInfo::getDestEquivalentVGPRClass(  in getDestEquivalentVGPRClass()
8492 Register SIInstrInfo::findUsedSGPR(const MachineInstr &MI,  in findUsedSGPR()
8562 MachineOperand *SIInstrInfo::getNamedOperand(MachineInstr &MI,  in getNamedOperand()
8571 uint64_t SIInstrInfo::getDefaultRsrcDataFormat() const {  in getDefaultRsrcDataFormat()
8596 uint64_t SIInstrInfo::getScratchRsrcWords23() const {  in getScratchRsrcWords23()
8620 bool SIInstrInfo::isLowLatencyInstruction(const MachineInstr &MI) const {  in isLowLatencyInstruction()
8626 bool SIInstrInfo::isHighLatencyDef(int Opc) const {  in isHighLatencyDef()
8631 unsigned SIInstrInfo::isStackAccess(const MachineInstr &MI,  in isStackAccess()
8644 unsigned SIInstrInfo::isSGPRStackAccess(const MachineInstr &MI,  in isSGPRStackAccess()
8652 Register SIInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,  in isLoadFromStackSlot()
8666 Register SIInstrInfo::isStoreToStackSlot(const MachineInstr &MI,  in isStoreToStackSlot()
8680 unsigned SIInstrInfo::getInstBundleSize(const MachineInstr &MI) const {  in getInstBundleSize()
8692 unsigned SIInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {  in getInstSizeInBytes()
8753 bool SIInstrInfo::mayAccessFlatAddressSpace(const MachineInstr &MI) const {  in mayAccessFlatAddressSpace()
8767 bool SIInstrInfo::isNonUniformBranchInstr(MachineInstr &Branch) const {  in isNonUniformBranchInstr()
8771 void SIInstrInfo::convertNonUniformIfRegion(MachineBasicBlock *IfEntry,  in convertNonUniformIfRegion()
8796 void SIInstrInfo::convertNonUniformLoopRegion(  in convertNonUniformLoopRegion()
8841 SIInstrInfo::getSerializableTargetIndices() const {  in getSerializableTargetIndices()
8854 SIInstrInfo::CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,  in CreateTargetPostRAHazardRecognizer()
8862 SIInstrInfo::CreateTargetPostRAHazardRecognizer(const MachineFunction &MF) const {  in CreateTargetPostRAHazardRecognizer()
8869 SIInstrInfo::CreateTargetMIHazardRecognizer(const InstrItineraryData *II,  in CreateTargetMIHazardRecognizer()
8881 SIInstrInfo::decomposeMachineOperandsTargetFlags(unsigned TF) const {  in decomposeMachineOperandsTargetFlags()
8886 SIInstrInfo::getSerializableDirectMachineOperandTargetFlags() const {  in getSerializableDirectMachineOperandTargetFlags()
8901 SIInstrInfo::getSerializableMachineMemOperandTargetFlags() const {  in getSerializableMachineMemOperandTargetFlags()
8911 unsigned SIInstrInfo::getLiveRangeSplitOpcode(Register SrcReg,  in getLiveRangeSplitOpcode()
8921 bool SIInstrInfo::isBasicBlockPrologue(const MachineInstr &MI,  in isBasicBlockPrologue()
8944 SIInstrInfo::getAddNoCarry(MachineBasicBlock &MBB,  in getAddNoCarry()
8959 MachineInstrBuilder SIInstrInfo::getAddNoCarry(MachineBasicBlock &MBB,  in getAddNoCarry()
8982 bool SIInstrInfo::isKillTerminator(unsigned Opcode) {  in isKillTerminator()
8992 const MCInstrDesc &SIInstrInfo::getKillTerminatorFromPseudo(unsigned Opcode) const {  in getKillTerminatorFromPseudo()
9003 bool SIInstrInfo::isLegalMUBUFImmOffset(unsigned Imm) const {  in isLegalMUBUFImmOffset()
9007 unsigned SIInstrInfo::getMaxMUBUFImmOffset(const GCNSubtarget &ST) {  in getMaxMUBUFImmOffset()
9014 void SIInstrInfo::fixImplicitOperands(MachineInstr &MI) const {  in fixImplicitOperands()
9027 bool SIInstrInfo::isBufferSMRD(const MachineInstr &MI) const {  in isBufferSMRD()
9047 bool SIInstrInfo::splitMUBUFOffset(uint32_t Imm, uint32_t &SOffset,  in splitMUBUFOffset()
9049   const uint32_t MaxOffset = SIInstrInfo::getMaxMUBUFImmOffset(ST);  in splitMUBUFOffset()
9123 bool SIInstrInfo::isLegalFLATOffset(int64_t Offset, unsigned AddrSpace,  in isLegalFLATOffset()
9147 SIInstrInfo::splitFlatOffset(int64_t COffsetVal, unsigned AddrSpace,  in splitFlatOffset()
9178 bool SIInstrInfo::allowNegativeFlatOffset(uint64_t FlatVariant) const {  in allowNegativeFlatOffset()
9206 bool SIInstrInfo::isAsmOnlyOpcode(int MCOp) const {  in isAsmOnlyOpcode()
9226 int SIInstrInfo::pseudoToMCOpcode(int Opcode) const {  in pseudoToMCOpcode()
9227   Opcode = SIInstrInfo::getNonSoftWaitcntOpcode(Opcode);  in pseudoToMCOpcode()
9459 MachineInstr *SIInstrInfo::createPHIDestinationCopy(  in createPHIDestinationCopy()
9474 MachineInstr *SIInstrInfo::createPHISourceCopy(  in createPHISourceCopy()
9494 bool llvm::SIInstrInfo::isWave32() const { return ST.isWave32(); }  in isWave32()
9496 MachineInstr *SIInstrInfo::foldMemoryOperandImpl(  in foldMemoryOperandImpl()
9534 unsigned SIInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,  in getInstrLatency()
9552 SIInstrInfo::getGenericInstructionUniformity(const MachineInstr &MI) const {  in getGenericInstructionUniformity()
9591   if (SIInstrInfo::isGenericAtomicRMWOpcode(opcode) ||  in getGenericInstructionUniformity()
9601 SIInstrInfo::getInstructionUniformity(const MachineInstr &MI) const {  in getInstructionUniformity()
9625     return SIInstrInfo::getGenericInstructionUniformity(MI);  in getInstructionUniformity()
9685 unsigned SIInstrInfo::getDSShaderTypeValue(const MachineFunction &MF) {  in getDSShaderTypeValue()
9707 bool SIInstrInfo::analyzeCompare(const MachineInstr &MI, Register &SrcReg,  in analyzeCompare()
9766 bool SIInstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg,  in optimizeCompareInstr()
9914 void SIInstrInfo::enforceOperandRCAlignment(MachineInstr &MI,  in enforceOperandRCAlignment()