Lines Matching full:const
33 const GCNSubtarget *Subtarget;
38 EVT VT) const override;
41 EVT VT) const override;
45 unsigned &NumIntermediates, MVT &RegisterVT) const override;
48 SDValue lowerKernArgParameterPtr(SelectionDAG &DAG, const SDLoc &SL,
49 SDValue Chain, uint64_t Offset) const;
50 SDValue getImplicitArgPtr(SelectionDAG &DAG, const SDLoc &SL) const;
51 SDValue getLDSKernelId(SelectionDAG &DAG, const SDLoc &SL) const;
53 const SDLoc &SL, SDValue Chain,
56 const ISD::InputArg *Arg = nullptr) const;
57 SDValue loadImplicitKernelArgument(SelectionDAG &DAG, MVT VT, const SDLoc &DL,
59 ImplicitParameter Param) const;
62 const SDLoc &SL, SDValue Chain,
63 const ISD::InputArg &Arg) const;
65 const SIMachineFunctionInfo &MFI,
67 AMDGPUFunctionArgInfo::PreloadedValue) const;
70 SelectionDAG &DAG) const override;
72 MVT VT, unsigned Offset) const;
73 SDValue lowerImage(SDValue Op, const AMDGPU::ImageDimIntrinsicInfo *Intr,
74 SelectionDAG &DAG, bool WithChain) const;
76 SDValue CachePolicy, SelectionDAG &DAG) const;
79 unsigned NewOpcode) const;
81 unsigned NewOpcode) const;
83 SDValue lowerWaveID(SelectionDAG &DAG, SDValue Op) const;
85 const ArgDescriptor &ArgDesc) const;
87 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
88 SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const;
89 SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const;
98 SelectionDAG &DAG) const;
100 SDValue widenLoad(LoadSDNode *Ld, DAGCombinerInfo &DCI) const;
101 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
102 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
103 SDValue lowerFastUnsafeFDIV(SDValue Op, SelectionDAG &DAG) const;
104 SDValue lowerFastUnsafeFDIV64(SDValue Op, SelectionDAG &DAG) const;
105 SDValue lowerFDIV_FAST(SDValue Op, SelectionDAG &DAG) const;
106 SDValue LowerFDIV16(SDValue Op, SelectionDAG &DAG) const;
107 SDValue LowerFDIV32(SDValue Op, SelectionDAG &DAG) const;
108 SDValue LowerFDIV64(SDValue Op, SelectionDAG &DAG) const;
109 SDValue LowerFDIV(SDValue Op, SelectionDAG &DAG) const;
110 SDValue LowerFFREXP(SDValue Op, SelectionDAG &DAG) const;
111 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
112 SDValue LowerTrig(SDValue Op, SelectionDAG &DAG) const;
113 SDValue lowerFSQRTF16(SDValue Op, SelectionDAG &DAG) const;
114 SDValue lowerFSQRTF32(SDValue Op, SelectionDAG &DAG) const;
115 SDValue lowerFSQRTF64(SDValue Op, SelectionDAG &DAG) const;
116 SDValue LowerATOMIC_CMP_SWAP(SDValue Op, SelectionDAG &DAG) const;
117 SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
118 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
121 bool IsIntrinsic = false) const;
124 ArrayRef<SDValue> Ops) const;
128 SDValue getMemIntrinsicNode(unsigned Opcode, const SDLoc &DL, SDVTList VTList,
130 MachineMemOperand *MMO, SelectionDAG &DAG) const;
133 bool ImageStore = false) const;
139 const SDLoc &DL,
140 EVT VT) const;
143 SelectionDAG &DAG, EVT VT, EVT MemVT, const SDLoc &SL, SDValue Val,
144 bool Signed, const ISD::InputArg *Arg = nullptr) const;
147 SDValue lowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const;
148 SDValue lowerFMINNUM_FMAXNUM(SDValue Op, SelectionDAG &DAG) const;
149 SDValue lowerFLDEXP(SDValue Op, SelectionDAG &DAG) const;
150 SDValue lowerMUL(SDValue Op, SelectionDAG &DAG) const;
151 SDValue lowerXMULO(SDValue Op, SelectionDAG &DAG) const;
152 SDValue lowerXMUL_LOHI(SDValue Op, SelectionDAG &DAG) const;
154 SDValue getSegmentAperture(unsigned AS, const SDLoc &DL,
155 SelectionDAG &DAG) const;
157 SDValue lowerADDRSPACECAST(SDValue Op, SelectionDAG &DAG) const;
158 SDValue lowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
159 SDValue lowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
160 SDValue lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
161 SDValue lowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
162 SDValue lowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const;
163 SDValue lowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
165 SDValue lowerTRAP(SDValue Op, SelectionDAG &DAG) const;
166 SDValue lowerTrapEndpgm(SDValue Op, SelectionDAG &DAG) const;
167 SDValue lowerTrapHsaQueuePtr(SDValue Op, SelectionDAG &DAG) const;
168 SDValue lowerTrapHsa(SDValue Op, SelectionDAG &DAG) const;
169 SDValue lowerDEBUGTRAP(SDValue Op, SelectionDAG &DAG) const;
171 SDNode *adjustWritemask(MachineSDNode *&N, SelectionDAG &DAG) const;
174 DAGCombinerInfo &DCI) const;
175 SDValue performFCopySignCombine(SDNode *N, DAGCombinerInfo &DCI) const;
180 DAGCombinerInfo &DCI) const;
182 SDValue performMemSDNodeCombine(MemSDNode *N, DAGCombinerInfo &DCI) const;
184 SDValue splitBinaryBitConstantOp(DAGCombinerInfo &DCI, const SDLoc &SL,
186 const ConstantSDNode *CRHS) const;
188 SDValue performAndCombine(SDNode *N, DAGCombinerInfo &DCI) const;
189 SDValue performOrCombine(SDNode *N, DAGCombinerInfo &DCI) const;
190 SDValue performXorCombine(SDNode *N, DAGCombinerInfo &DCI) const;
191 SDValue performZeroExtendCombine(SDNode *N, DAGCombinerInfo &DCI) const;
192 SDValue performSignExtendInRegCombine(SDNode *N, DAGCombinerInfo &DCI) const;
193 SDValue performClassCombine(SDNode *N, DAGCombinerInfo &DCI) const;
194 SDValue getCanonicalConstantFP(SelectionDAG &DAG, const SDLoc &SL, EVT VT,
195 const APFloat &C) const;
196 SDValue performFCanonicalizeCombine(SDNode *N, DAGCombinerInfo &DCI) const;
198 SDValue performFPMed3ImmCombine(SelectionDAG &DAG, const SDLoc &SL,
199 SDValue Op0, SDValue Op1) const;
200 SDValue performIntMed3ImmCombine(SelectionDAG &DAG, const SDLoc &SL,
202 bool Signed) const;
203 SDValue performMinMaxCombine(SDNode *N, DAGCombinerInfo &DCI) const;
204 SDValue performFMed3Combine(SDNode *N, DAGCombinerInfo &DCI) const;
205 SDValue performCvtPkRTZCombine(SDNode *N, DAGCombinerInfo &DCI) const;
206 SDValue performExtractVectorEltCombine(SDNode *N, DAGCombinerInfo &DCI) const;
207 SDValue performInsertVectorEltCombine(SDNode *N, DAGCombinerInfo &DCI) const;
208 SDValue performFPRoundCombine(SDNode *N, DAGCombinerInfo &DCI) const;
210 SDValue reassociateScalarOps(SDNode *N, SelectionDAG &DAG) const;
211 unsigned getFusedOpcode(const SelectionDAG &DAG,
212 const SDNode *N0, const SDNode *N1) const;
213 SDValue tryFoldToMad64_32(SDNode *N, DAGCombinerInfo &DCI) const;
214 SDValue performAddCombine(SDNode *N, DAGCombinerInfo &DCI) const;
215 SDValue performAddCarrySubCarryCombine(SDNode *N, DAGCombinerInfo &DCI) const;
216 SDValue performSubCombine(SDNode *N, DAGCombinerInfo &DCI) const;
217 SDValue performFAddCombine(SDNode *N, DAGCombinerInfo &DCI) const;
218 SDValue performFSubCombine(SDNode *N, DAGCombinerInfo &DCI) const;
219 SDValue performFDivCombine(SDNode *N, DAGCombinerInfo &DCI) const;
220 SDValue performFMACombine(SDNode *N, DAGCombinerInfo &DCI) const;
221 SDValue performSetCCCombine(SDNode *N, DAGCombinerInfo &DCI) const;
222 SDValue performCvtF32UByteNCombine(SDNode *N, DAGCombinerInfo &DCI) const;
223 SDValue performClampCombine(SDNode *N, DAGCombinerInfo &DCI) const;
224 SDValue performRcpCombine(SDNode *N, DAGCombinerInfo &DCI) const;
226 bool isLegalMUBUFAddressingMode(const AddrMode &AM) const;
228 unsigned isCFIntrinsic(const SDNode *Intr) const;
233 bool shouldEmitFixup(const GlobalValue *GV) const;
237 bool shouldEmitGOTReloc(const GlobalValue *GV) const;
241 bool shouldEmitPCReloc(const GlobalValue *GV) const;
245 bool shouldUseLDSConstAddress(const GlobalValue *GV) const;
251 const GCNSubtarget *Subtarget);
253 bool shouldExpandVectorDynExt(SDNode *N) const;
260 SDValue *Offsets, Align Alignment = Align(4)) const;
267 SDValue bufferRsrcPtrToVector(SDValue MaybePointer, SelectionDAG &DAG) const;
271 SDValue lowerPointerAsRsrcIntrin(SDNode *Op, SelectionDAG &DAG) const;
277 bool IsTFE = false) const;
282 MemSDNode *M) const;
285 SITargetLowering(const TargetMachine &tm, const GCNSubtarget &STI);
287 const GCNSubtarget *getSubtarget() const;
289 ArrayRef<MCPhysReg> getRoundingControlRegisters() const override;
291 bool isFPExtFoldable(const SelectionDAG &DAG, unsigned Opcode, EVT DestVT,
292 EVT SrcVT) const override;
294 bool isFPExtFoldable(const MachineInstr &MI, unsigned Opcode, LLT DestTy,
295 LLT SrcTy) const override;
297 bool isShuffleMaskLegal(ArrayRef<int> /*Mask*/, EVT /*VT*/) const override;
302 MVT getPointerTy(const DataLayout &DL, unsigned AS) const override;
303 MVT getPointerMemTy(const DataLayout &DL, unsigned AS) const override;
305 bool getTgtMemIntrinsic(IntrinsicInfo &, const CallInst &,
307 unsigned IntrinsicID) const override;
309 void CollectTargetIntrinsicOperands(const CallInst &I,
311 SelectionDAG &DAG) const override;
315 Type *&/*AccessTy*/) const override;
317 bool isLegalFlatAddressingMode(const AddrMode &AM, unsigned AddrSpace) const;
318 bool isLegalGlobalAddressingMode(const AddrMode &AM) const;
319 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
321 Instruction *I = nullptr) const override;
324 const MachineFunction &MF) const override;
329 unsigned *IsFast = nullptr) const;
334 unsigned *IsFast = nullptr) const override {
344 unsigned *IsFast = nullptr) const override;
346 EVT getOptimalMemOpType(const MemOp &Op,
347 const AttributeList &FuncAttributes) const override;
349 bool isMemOpUniform(const SDNode *N) const;
350 bool isMemOpHasNoClobberedMemOperand(const SDNode *N) const;
354 bool isFreeAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override;
357 getPreferredVectorAction(MVT VT) const override;
359 bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
360 Type *Ty) const override;
363 unsigned Index) const override;
365 bool isTypeDesirableForOp(unsigned Op, EVT VT) const override;
367 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
369 unsigned combineRepeatedFPDivisors() const override { in combineRepeatedFPDivisors()
375 bool supportSplitCSR(MachineFunction *MF) const override;
376 void initializeSplitCSR(MachineBasicBlock *Entry) const override;
379 const SmallVectorImpl<MachineBasicBlock *> &Exits) const override;
383 const SmallVectorImpl<ISD::InputArg> &Ins,
384 const SDLoc &DL, SelectionDAG &DAG,
385 SmallVectorImpl<SDValue> &InVals) const override;
389 const SmallVectorImpl<ISD::OutputArg> &Outs,
390 LLVMContext &Context) const override;
393 const SmallVectorImpl<ISD::OutputArg> &Outs,
394 const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
395 SelectionDAG &DAG) const override;
400 const SIMachineFunctionInfo &Info,
403 SDValue Chain) const;
407 const SmallVectorImpl<ISD::InputArg> &Ins,
408 const SDLoc &DL, SelectionDAG &DAG,
410 SDValue ThisVal) const;
412 bool mayBeEmittedAsTailCall(const CallInst *) const override;
416 const SmallVectorImpl<ISD::OutputArg> &Outs,
417 const SmallVectorImpl<SDValue> &OutVals,
418 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const;
421 SmallVectorImpl<SDValue> &InVals) const override;
423 SDValue lowerDYNAMIC_STACKALLOCImpl(SDValue Op, SelectionDAG &DAG) const;
424 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
425 SDValue LowerSTACKSAVE(SDValue Op, SelectionDAG &DAG) const;
426 SDValue lowerGET_ROUNDING(SDValue Op, SelectionDAG &DAG) const;
427 SDValue lowerSET_ROUNDING(SDValue Op, SelectionDAG &DAG) const;
429 SDValue lowerPREFETCH(SDValue Op, SelectionDAG &DAG) const;
430 SDValue lowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const;
431 SDValue lowerGET_FPENV(SDValue Op, SelectionDAG &DAG) const;
432 SDValue lowerSET_FPENV(SDValue Op, SelectionDAG &DAG) const;
434 Register getRegisterByName(const char* RegName, LLT VT,
435 const MachineFunction &MF) const override;
438 MachineBasicBlock *BB) const;
440 void bundleInstWithWaitcnt(MachineInstr &MI) const;
442 MachineBasicBlock *BB) const;
446 MachineBasicBlock *BB) const override;
448 bool enableAggressiveFMAFusion(EVT VT) const override;
449 bool enableAggressiveFMAFusion(LLT Ty) const override;
450 EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
451 EVT VT) const override;
452 MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override;
453 LLT getPreferredShiftAmountTy(LLT Ty) const override;
455 bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF,
456 EVT VT) const override;
457 bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF,
458 const LLT Ty) const override;
459 bool isFMADLegal(const SelectionDAG &DAG, const SDNode *N) const override;
460 bool isFMADLegal(const MachineInstr &MI, const LLT Ty) const override;
462 SDValue splitUnaryVectorOp(SDValue Op, SelectionDAG &DAG) const;
463 SDValue splitBinaryVectorOp(SDValue Op, SelectionDAG &DAG) const;
464 SDValue splitTernaryVectorOp(SDValue Op, SelectionDAG &DAG) const;
465 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
468 SelectionDAG &DAG) const override;
470 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
471 SDNode *PostISelFolding(MachineSDNode *N, SelectionDAG &DAG) const override;
472 void AddMemOpInit(MachineInstr &MI) const;
474 SDNode *Node) const override;
476 SDNode *legalizeTargetIndependentNode(SDNode *Node, SelectionDAG &DAG) const;
478 MachineSDNode *wrapAddr64Rsrc(SelectionDAG &DAG, const SDLoc &DL,
479 SDValue Ptr) const;
480 MachineSDNode *buildRSRC(SelectionDAG &DAG, const SDLoc &DL, SDValue Ptr,
481 uint32_t RsrcDword1, uint64_t RsrcDword2And3) const;
482 std::pair<unsigned, const TargetRegisterClass *>
483 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
484 StringRef Constraint, MVT VT) const override;
485 ConstraintType getConstraintType(StringRef Constraint) const override;
488 SelectionDAG &DAG) const override;
489 bool getAsmOperandConstVal(SDValue Op, uint64_t &Val) const;
491 uint64_t Val) const;
494 unsigned MaxSize = 64) const;
495 SDValue copyToM0(SelectionDAG &DAG, SDValue Chain, const SDLoc &DL,
496 SDValue V) const;
498 void finalizeLowering(MachineFunction &MF) const override;
500 void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known,
501 const APInt &DemandedElts,
502 const SelectionDAG &DAG,
503 unsigned Depth = 0) const override;
506 const MachineFunction &MF) const override;
509 const APInt &DemandedElts,
510 const MachineRegisterInfo &MRI,
511 unsigned Depth = 0) const override;
514 const MachineRegisterInfo &MRI,
515 unsigned Depth = 0) const override;
516 bool isSDNodeSourceOfDivergence(const SDNode *N, FunctionLoweringInfo *FLI,
517 UniformityInfo *UA) const override;
519 bool hasMemSDNodeUser(SDNode *N) const;
522 SDValue N1) const override;
525 Register N1) const override;
528 unsigned MaxDepth = 5) const;
529 bool isCanonicalized(Register Reg, const MachineFunction &MF,
530 unsigned MaxDepth = 5) const;
531 bool denormalsEnabledForType(const SelectionDAG &DAG, EVT VT) const;
532 bool denormalsEnabledForType(LLT Ty, const MachineFunction &MF) const;
535 const TargetRegisterInfo *TRI,
536 const TargetInstrInfo *TII, unsigned &PhysReg,
537 int &Cost) const override;
540 const SelectionDAG &DAG,
542 unsigned Depth = 0) const override;
543 AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *) const override;
544 AtomicExpansionKind shouldExpandAtomicLoadInIR(LoadInst *LI) const override;
545 AtomicExpansionKind shouldExpandAtomicStoreInIR(StoreInst *SI) const override;
547 shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const override;
548 void emitExpandAtomicRMW(AtomicRMWInst *AI) const override;
551 lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *AI) const override;
553 const TargetRegisterClass *getRegClassFor(MVT VT,
554 bool isDivergent) const override;
556 const Value *V) const override;
557 Align getPrefLoopAlignment(MachineLoop *ML) const override;
561 const SIRegisterInfo &TRI,
562 SIMachineFunctionInfo &Info) const;
566 const SmallVectorImpl<ISD::InputArg> &Ins,
568 const SIRegisterInfo &TRI,
569 SIMachineFunctionInfo &Info) const;
572 const SIRegisterInfo &TRI,
573 SIMachineFunctionInfo &Info) const;
579 bool IsShader) const;
583 const SIRegisterInfo &TRI,
584 SIMachineFunctionInfo &Info) const;
588 const SIRegisterInfo &TRI,
589 SIMachineFunctionInfo &Info) const;
593 const SIRegisterInfo &TRI,
594 SIMachineFunctionInfo &Info) const;
597 const SIRegisterInfo &TRI,
598 SIMachineFunctionInfo &Info) const;
601 getTargetMMOFlags(const Instruction &I) const override;