Lines Matching refs:SGPRIdxReg
4465 Register &SGPRIdxReg) { in emitLoadM0FromVGPRLoop() argument
4509 SGPRIdxReg = CurrentIdxReg; in emitLoadM0FromVGPRLoop()
4511 SGPRIdxReg = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass); in emitLoadM0FromVGPRLoop()
4512 BuildMI(LoopBB, I, DL, TII->get(AMDGPU::S_ADD_I32), SGPRIdxReg) in emitLoadM0FromVGPRLoop()
4554 bool UseGPRIdxMode, Register &SGPRIdxReg) { in loadM0FromVGPR() argument
4583 Offset, UseGPRIdxMode, SGPRIdxReg); in loadM0FromVGPR()
4715 Register SGPRIdxReg; in emitIndirectSrc() local
4717 UseGPRIdxMode, SGPRIdxReg); in emitIndirectSrc()
4727 .addReg(SGPRIdxReg) in emitIndirectSrc()
4817 Register SGPRIdxReg; in emitIndirectDst() local
4819 UseGPRIdxMode, SGPRIdxReg); in emitIndirectDst()
4829 .addReg(SGPRIdxReg) in emitIndirectDst()