Lines Matching refs:DCI
7287 DAGCombinerInfo DCI(DAG, AfterLegalizeVectorOps, true, nullptr); in lowerEXTRACT_VECTOR_ELT() local
7293 if (SDValue Combined = performExtractVectorEltCombine(Op.getNode(), DCI)) in lowerEXTRACT_VECTOR_ELT()
10174 SDValue SITargetLowering::widenLoad(LoadSDNode *Ld, DAGCombinerInfo &DCI) const { in widenLoad()
10175 SelectionDAG &DAG = DCI.DAG; in widenLoad()
10190 if ((MemVT.isSimple() && !DCI.isAfterLegalizeDAG()) || in widenLoad()
10228 DCI.AddToWorklist(Cvt.getNode()); in widenLoad()
10233 DCI.AddToWorklist(Cvt.getNode()); in widenLoad()
11209 DAGCombinerInfo &DCI) const { in performUCharToFloatCombine()
11215 SelectionDAG &DAG = DCI.DAG; in performUCharToFloatCombine()
11225 if (DCI.isAfterLegalizeDAG() && SrcVT == MVT::i32) { in performUCharToFloatCombine()
11228 DCI.AddToWorklist(Cvt.getNode()); in performUCharToFloatCombine()
11243 DAGCombinerInfo &DCI) const { in performFCopySignCombine()
11246 SelectionDAG &DAG = DCI.DAG; in performFCopySignCombine()
11305 DAGCombinerInfo &DCI) const { in performSHLPtrCombine()
11323 SelectionDAG &DAG = DCI.DAG; in performSHLPtrCombine()
11332 Type *Ty = MemVT.getTypeForEVT(*DCI.DAG.getContext()); in performSHLPtrCombine()
11337 if (!isLegalAddressingMode(DCI.DAG.getDataLayout(), AM, Ty, AddrSpace)) in performSHLPtrCombine()
11369 DAGCombinerInfo &DCI) const { in performMemSDNodeCombine()
11370 SelectionDAG &DAG = DCI.DAG; in performMemSDNodeCombine()
11379 N->getMemoryVT(), DCI); in performMemSDNodeCombine()
11403 DAGCombinerInfo &DCI, in splitBinaryBitConstantOp() argument
11418 return splitBinaryBitConstantOpImpl(DCI, SL, Opc, LHS, ValLo, ValHi); in splitBinaryBitConstantOp()
11505 DAGCombinerInfo &DCI) const { in performAndCombine()
11506 if (DCI.isBeforeLegalize()) in performAndCombine()
11509 SelectionDAG &DAG = DCI.DAG; in performAndCombine()
11518 = splitBinaryBitConstantOp(DCI, SDLoc(N), ISD::AND, LHS, CRHS)) in performAndCombine()
12183 static SDValue matchPERM(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) { in matchPERM() argument
12184 SelectionDAG &DAG = DCI.DAG; in matchPERM()
12275 DAGCombinerInfo &DCI) const { in performOrCombine()
12276 SelectionDAG &DAG = DCI.DAG; in performOrCombine()
12387 if (SDValue Perm = matchPERM(N, DCI)) in performOrCombine()
12392 if (VT != MVT::i64 || DCI.isBeforeLegalizeOps()) in performOrCombine()
12413 DCI.AddToWorklist(LowOr.getNode()); in performOrCombine()
12414 DCI.AddToWorklist(HiBits.getNode()); in performOrCombine()
12425 = splitBinaryBitConstantOp(DCI, SDLoc(N), ISD::OR, in performOrCombine()
12434 DAGCombinerInfo &DCI) const { in performXorCombine()
12435 if (SDValue RV = reassociateScalarOps(N, DCI.DAG)) in performXorCombine()
12442 SelectionDAG &DAG = DCI.DAG; in performXorCombine()
12447 = splitBinaryBitConstantOp(DCI, SDLoc(N), ISD::XOR, LHS, CRHS)) in performXorCombine()
12476 DAGCombinerInfo &DCI) const { in performZeroExtendCombine()
12478 DCI.getDAGCombineLevel() < AfterLegalizeDAG) in performZeroExtendCombine()
12494 DAGCombinerInfo &DCI) const { in performSignExtendInRegCombine()
12512 SDVTList ResList = DCI.DAG.getVTList(MVT::i32); in performSignExtendInRegCombine()
12519 SDValue BufferLoad = DCI.DAG.getMemIntrinsicNode( in performSignExtendInRegCombine()
12521 SDValue LoadVal = DCI.DAG.getNode(ISD::TRUNCATE, DL, VT, BufferLoad); in performSignExtendInRegCombine()
12541 SDVTList ResList = DCI.DAG.getVTList(MVT::i32, in performSignExtendInRegCombine()
12545 SDValue BufferLoadSignExt = DCI.DAG.getMemIntrinsicNode(Opc, SDLoc(N), in performSignExtendInRegCombine()
12549 return DCI.DAG.getMergeValues({BufferLoadSignExt, in performSignExtendInRegCombine()
12556 DAGCombinerInfo &DCI) const { in performClassCombine()
12557 SelectionDAG &DAG = DCI.DAG; in performClassCombine()
12571 DAGCombinerInfo &DCI) const { in performRcpCombine()
12576 return DCI.DAG.getConstantFP( in performRcpCombine()
12583 return DCI.DAG.getNode(AMDGPUISD::RCP_IFLAG, SDLoc(N), VT, N0, in performRcpCombine()
12590 return DCI.DAG.getNode(AMDGPUISD::RSQ, SDLoc(N), VT, in performRcpCombine()
12594 return AMDGPUTargetLowering::performRcpCombine(N, DCI); in performRcpCombine()
12955 DAGCombinerInfo &DCI) const { in performFCanonicalizeCombine()
12956 SelectionDAG &DAG = DCI.DAG; in performFCanonicalizeCombine()
13175 DAGCombinerInfo &DCI) const { in performMinMaxCombine()
13176 SelectionDAG &DAG = DCI.DAG; in performMinMaxCombine()
13267 DAGCombinerInfo &DCI) const { in performFMed3Combine()
13272 SelectionDAG &DAG = DCI.DAG; in performFMed3Combine()
13311 DAGCombinerInfo &DCI) const { in performCvtPkRTZCombine()
13315 return DCI.DAG.getUNDEF(N->getValueType(0)); in performCvtPkRTZCombine()
13373 SDNode *N, DAGCombinerInfo &DCI) const { in performExtractVectorEltCombine()
13375 SelectionDAG &DAG = DCI.DAG; in performExtractVectorEltCombine()
13398 if (Vec.hasOneUse() && DCI.isBeforeLegalize() && VecEltVT == ResVT) { in performExtractVectorEltCombine()
13426 DCI.AddToWorklist(Elt0.getNode()); in performExtractVectorEltCombine()
13427 DCI.AddToWorklist(Elt1.getNode()); in performExtractVectorEltCombine()
13449 if (!DCI.isBeforeLegalize()) in performExtractVectorEltCombine()
13466 DCI.AddToWorklist(Cast.getNode()); in performExtractVectorEltCombine()
13470 DCI.AddToWorklist(Elt.getNode()); in performExtractVectorEltCombine()
13473 DCI.AddToWorklist(Srl.getNode()); in performExtractVectorEltCombine()
13477 DCI.AddToWorklist(Trunc.getNode()); in performExtractVectorEltCombine()
13492 DAGCombinerInfo &DCI) const { in performInsertVectorEltCombine()
13503 SelectionDAG &DAG = DCI.DAG; in performInsertVectorEltCombine()
13539 DAGCombinerInfo &DCI) const { in performFPRoundCombine()
13552 SelectionDAG &DAG = DCI.DAG; in performFPRoundCombine()
13664 DAGCombinerInfo &DCI) const { in tryFoldToMad64_32()
13667 SelectionDAG &DAG = DCI.DAG; in tryFoldToMad64_32()
14041 DAGCombinerInfo &DCI) const { in performAddCombine()
14042 SelectionDAG &DAG = DCI.DAG; in performAddCombine()
14050 if (SDValue Folded = tryFoldToMad64_32(N, DCI)) in performAddCombine()
14201 if (VT != MVT::i32 || !DCI.isAfterLegalizeDAG()) in performAddCombine()
14239 DAGCombinerInfo &DCI) const { in performSubCombine()
14240 SelectionDAG &DAG = DCI.DAG; in performSubCombine()
14281 DAGCombinerInfo &DCI) const { in performAddCarrySubCarryCombine()
14289 SelectionDAG &DAG = DCI.DAG; in performAddCarrySubCarryCombine()
14305 DAGCombinerInfo &DCI) const { in performFAddCombine()
14306 if (DCI.getDAGCombineLevel() < AfterLegalizeDAG) in performFAddCombine()
14309 SelectionDAG &DAG = DCI.DAG; in performFAddCombine()
14347 DAGCombinerInfo &DCI) const { in performFSubCombine()
14348 if (DCI.getDAGCombineLevel() < AfterLegalizeDAG) in performFSubCombine()
14351 SelectionDAG &DAG = DCI.DAG; in performFSubCombine()
14394 DAGCombinerInfo &DCI) const { in performFDivCombine()
14395 SelectionDAG &DAG = DCI.DAG; in performFDivCombine()
14429 DAGCombinerInfo &DCI) const { in performFMACombine()
14430 SelectionDAG &DAG = DCI.DAG; in performFMACombine()
14504 DAGCombinerInfo &DCI) const { in performSetCCCombine()
14505 SelectionDAG &DAG = DCI.DAG; in performSetCCCombine()
14600 DAGCombinerInfo &DCI) const { in performCvtF32UByteNCombine()
14601 SelectionDAG &DAG = DCI.DAG; in performCvtF32UByteNCombine()
14637 if (TLI.SimplifyDemandedBits(Src, DemandedBits, DCI)) { in performCvtF32UByteNCombine()
14641 DCI.AddToWorklist(N); in performCvtF32UByteNCombine()
14654 DAGCombinerInfo &DCI) const { in performClampCombine()
14659 const MachineFunction &MF = DCI.DAG.getMachineFunction(); in performClampCombine()
14664 return DCI.DAG.getConstantFP(Zero, SDLoc(N), N->getValueType(0)); in performClampCombine()
14669 return DCI.DAG.getConstantFP(One, SDLoc(N), N->getValueType(0)); in performClampCombine()
14676 DAGCombinerInfo &DCI) const { in PerformDAGCombine()
14681 return performAddCombine(N, DCI); in PerformDAGCombine()
14683 return performSubCombine(N, DCI); in PerformDAGCombine()
14686 return performAddCarrySubCarryCombine(N, DCI); in PerformDAGCombine()
14688 return performFAddCombine(N, DCI); in PerformDAGCombine()
14690 return performFSubCombine(N, DCI); in PerformDAGCombine()
14692 return performFDivCombine(N, DCI); in PerformDAGCombine()
14694 return performSetCCCombine(N, DCI); in PerformDAGCombine()
14707 return performMinMaxCombine(N, DCI); in PerformDAGCombine()
14709 return performFMACombine(N, DCI); in PerformDAGCombine()
14711 return performAndCombine(N, DCI); in PerformDAGCombine()
14713 return performOrCombine(N, DCI); in PerformDAGCombine()
14718 return matchPERM(N, DCI); in PerformDAGCombine()
14723 return performXorCombine(N, DCI); in PerformDAGCombine()
14725 return performZeroExtendCombine(N, DCI); in PerformDAGCombine()
14727 return performSignExtendInRegCombine(N , DCI); in PerformDAGCombine()
14729 return performClassCombine(N, DCI); in PerformDAGCombine()
14731 return performFCanonicalizeCombine(N, DCI); in PerformDAGCombine()
14733 return performRcpCombine(N, DCI); in PerformDAGCombine()
14748 return performUCharToFloatCombine(N, DCI); in PerformDAGCombine()
14750 return performFCopySignCombine(N, DCI); in PerformDAGCombine()
14755 return performCvtF32UByteNCombine(N, DCI); in PerformDAGCombine()
14757 return performFMed3Combine(N, DCI); in PerformDAGCombine()
14759 return performCvtPkRTZCombine(N, DCI); in PerformDAGCombine()
14761 return performClampCombine(N, DCI); in PerformDAGCombine()
14763 SelectionDAG &DAG = DCI.DAG; in PerformDAGCombine()
14781 return performExtractVectorEltCombine(N, DCI); in PerformDAGCombine()
14783 return performInsertVectorEltCombine(N, DCI); in PerformDAGCombine()
14785 return performFPRoundCombine(N, DCI); in PerformDAGCombine()
14787 if (SDValue Widened = widenLoad(cast<LoadSDNode>(N), DCI)) in PerformDAGCombine()
14792 if (!DCI.isBeforeLegalize()) { in PerformDAGCombine()
14794 return performMemSDNodeCombine(MemNode, DCI); in PerformDAGCombine()
14801 return AMDGPUTargetLowering::PerformDAGCombine(N, DCI); in PerformDAGCombine()