74 static unsigned findFirstFreeSGPR(CCState &CCInfo) {  in findFirstFreeSGPR()  argument
77     if (!CCInfo.isAllocated(AMDGPU::SGPR0 + Reg)) {  in findFirstFreeSGPR()
2241 void SITargetLowering::allocateSpecialEntryInputVGPRs(CCState &CCInfo,  in allocateSpecialEntryInputVGPRs()  argument
2252     CCInfo.AllocateReg(Reg);  in allocateSpecialEntryInputVGPRs()
2267       CCInfo.AllocateReg(Reg);  in allocateSpecialEntryInputVGPRs()
2281       CCInfo.AllocateReg(Reg);  in allocateSpecialEntryInputVGPRs()
2291 static ArgDescriptor allocateVGPR32Input(CCState &CCInfo, unsigned Mask = ~0u,  in allocateVGPR32Input()  argument
2297   unsigned RegIdx = CCInfo.getFirstUnallocated(ArgVGPRs);  in allocateVGPR32Input()
2300     int64_t Offset = CCInfo.AllocateStack(4, Align(4));  in allocateVGPR32Input()
2306   Reg = CCInfo.AllocateReg(Reg);  in allocateVGPR32Input()
2309   MachineFunction &MF = CCInfo.getMachineFunction();  in allocateVGPR32Input()
2315 static ArgDescriptor allocateSGPR32InputImpl(CCState &CCInfo,  in allocateSGPR32InputImpl()  argument
2319   unsigned RegIdx = CCInfo.getFirstUnallocated(ArgSGPRs);  in allocateSGPR32InputImpl()
2324   Reg = CCInfo.AllocateReg(Reg);  in allocateSGPR32InputImpl()
2327   MachineFunction &MF = CCInfo.getMachineFunction();  in allocateSGPR32InputImpl()
2335 static void allocateFixedSGPRInputImpl(CCState &CCInfo,  in allocateFixedSGPRInputImpl()  argument
2338   Reg = CCInfo.AllocateReg(Reg);  in allocateFixedSGPRInputImpl()
2340   MachineFunction &MF = CCInfo.getMachineFunction();  in allocateFixedSGPRInputImpl()
2344 static void allocateSGPR32Input(CCState &CCInfo, ArgDescriptor &Arg) {  in allocateSGPR32Input()  argument
2346     allocateFixedSGPRInputImpl(CCInfo, &AMDGPU::SGPR_32RegClass,  in allocateSGPR32Input()
2349     Arg = allocateSGPR32InputImpl(CCInfo, &AMDGPU::SGPR_32RegClass, 32);  in allocateSGPR32Input()
2352 static void allocateSGPR64Input(CCState &CCInfo, ArgDescriptor &Arg) {  in allocateSGPR64Input()  argument
2354     allocateFixedSGPRInputImpl(CCInfo, &AMDGPU::SGPR_64RegClass,  in allocateSGPR64Input()
2357     Arg = allocateSGPR32InputImpl(CCInfo, &AMDGPU::SGPR_64RegClass, 16);  in allocateSGPR64Input()
2363   CCState &CCInfo, MachineFunction &MF,  in allocateSpecialInputVGPRs()  argument
2369     Arg = allocateVGPR32Input(CCInfo, Mask);  in allocateSpecialInputVGPRs()
2374     Arg = allocateVGPR32Input(CCInfo, Mask << 10, Arg);  in allocateSpecialInputVGPRs()
2379     Info.setWorkItemIDZ(allocateVGPR32Input(CCInfo, Mask << 20, Arg));  in allocateSpecialInputVGPRs()
2384   CCState &CCInfo, MachineFunction &MF,  in allocateSpecialInputVGPRsFixed()  argument
2386   Register Reg = CCInfo.AllocateReg(AMDGPU::VGPR31);  in allocateSpecialInputVGPRsFixed()
2397   CCState &CCInfo,  in allocateSpecialInputSGPRs()  argument
2406     allocateSGPR64Input(CCInfo, ArgInfo.DispatchPtr);  in allocateSpecialInputSGPRs()
2411     allocateSGPR64Input(CCInfo, ArgInfo.QueuePtr);  in allocateSpecialInputSGPRs()
2416     allocateSGPR64Input(CCInfo, ArgInfo.ImplicitArgPtr);  in allocateSpecialInputSGPRs()
2419     allocateSGPR64Input(CCInfo, ArgInfo.DispatchID);  in allocateSpecialInputSGPRs()
2424     allocateSGPR32Input(CCInfo, ArgInfo.WorkGroupIDX);  in allocateSpecialInputSGPRs()
2427     allocateSGPR32Input(CCInfo, ArgInfo.WorkGroupIDY);  in allocateSpecialInputSGPRs()
2430     allocateSGPR32Input(CCInfo, ArgInfo.WorkGroupIDZ);  in allocateSpecialInputSGPRs()
2433     allocateSGPR32Input(CCInfo, ArgInfo.LDSKernelId);  in allocateSpecialInputSGPRs()
2437 void SITargetLowering::allocateHSAUserSGPRs(CCState &CCInfo,  in allocateHSAUserSGPRs()  argument
2445     CCInfo.AllocateReg(ImplicitBufferPtrReg);  in allocateHSAUserSGPRs()
2452     CCInfo.AllocateReg(PrivateSegmentBufferReg);  in allocateHSAUserSGPRs()
2458     CCInfo.AllocateReg(DispatchPtrReg);  in allocateHSAUserSGPRs()
2466     CCInfo.AllocateReg(QueuePtrReg);  in allocateHSAUserSGPRs()
2472     CCInfo.AllocateReg(InputPtrReg);  in allocateHSAUserSGPRs()
2481     CCInfo.AllocateReg(DispatchIDReg);  in allocateHSAUserSGPRs()
2487     CCInfo.AllocateReg(FlatScratchInitReg);  in allocateHSAUserSGPRs()
2493     CCInfo.AllocateReg(PrivateSegmentSizeReg);  in allocateHSAUserSGPRs()
2503     CCState &CCInfo, SmallVectorImpl<CCValAssign> &ArgLocs,  in allocatePreloadKernArgSGPRs()  argument
2561         CCInfo.AllocateReg(Reg);  in allocatePreloadKernArgSGPRs()
2569 void SITargetLowering::allocateLDSKernelId(CCState &CCInfo, MachineFunction &MF,  in allocateLDSKernelId()  argument
2576     CCInfo.AllocateReg(Reg);  in allocateLDSKernelId()
2581 void SITargetLowering::allocateSystemSGPRs(CCState &CCInfo,  in allocateSystemSGPRs()  argument
2606       CCInfo.AllocateReg(Reg);  in allocateSystemSGPRs()
2614       CCInfo.AllocateReg(Reg);  in allocateSystemSGPRs()
2620       CCInfo.AllocateReg(Reg);  in allocateSystemSGPRs()
2626       CCInfo.AllocateReg(Reg);  in allocateSystemSGPRs()
2633     CCInfo.AllocateReg(Reg);  in allocateSystemSGPRs()
2647         PrivateSegmentWaveByteOffsetReg = findFirstFreeSGPR(CCInfo);  in allocateSystemSGPRs()
2654     CCInfo.AllocateReg(PrivateSegmentWaveByteOffsetReg);  in allocateSystemSGPRs()
2816   CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,  in LowerFormalArguments()  local
2857       CCInfo.AllocateReg(AMDGPU::VGPR0);  in LowerFormalArguments()
2858       CCInfo.AllocateReg(AMDGPU::VGPR1);  in LowerFormalArguments()
2883     analyzeFormalArgumentsCompute(CCInfo, Ins);  in LowerFormalArguments()
2886     allocateSpecialEntryInputVGPRs(CCInfo, MF, *TRI, *Info);  in LowerFormalArguments()
2887     allocateHSAUserSGPRs(CCInfo, MF, *TRI, *Info);  in LowerFormalArguments()
2889       allocatePreloadKernArgSGPRs(CCInfo, ArgLocs, Ins, MF, *TRI, *Info);  in LowerFormalArguments()
2891     allocateLDSKernelId(CCInfo, MF, *TRI, *Info);  in LowerFormalArguments()
2894     allocateSpecialInputVGPRsFixed(CCInfo, MF, *TRI, *Info);  in LowerFormalArguments()
2898       CCInfo.AllocateReg(Info->getScratchRSrcReg());  in LowerFormalArguments()
2900     allocateSpecialInputSGPRs(CCInfo, MF, *TRI, *Info);  in LowerFormalArguments()
2905     CCInfo.AnalyzeFormalArguments(Splits, AssignFn);  in LowerFormalArguments()
3114     allocateSystemSGPRs(CCInfo, MF, *Info, CallConv, IsGraphics);  in LowerFormalArguments()
3123   unsigned StackArgSize = CCInfo.getStackSize();  in LowerFormalArguments()
3144   CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context);  in CanLowerReturn()  local
3145   if (!CCInfo.CheckReturn(Outs, CCAssignFnForReturn(CallConv, IsVarArg)))  in CanLowerReturn()
3152     if (CCInfo.isAllocated(AMDGPU::VGPR_32RegClass.getRegister(i)))  in CanLowerReturn()
3182   CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,  in LowerReturn()  local
3186   CCInfo.AnalyzeReturn(Outs, CCAssignFnForReturn(CallConv, isVarArg));  in LowerReturn()
3262   CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,  in LowerCallResult()  local
3264   CCInfo.AnalyzeCallResult(Ins, RetCC);  in LowerCallResult()
3312     CCState &CCInfo,  in passSpecialInputs()  argument
3405       if (!CCInfo.AllocateReg(OutgoingArg->getRegister()))  in passSpecialInputs()
3409           CCInfo.AllocateStack(ArgVT.getStoreSize(), Align(4));  in passSpecialInputs()
3497     CCInfo.AllocateReg(OutgoingArg->getRegister());  in passSpecialInputs()
3499     unsigned SpecialArgOffset = CCInfo.AllocateStack(4, Align(4));  in passSpecialInputs()
3587   CCState CCInfo(CalleeCC, IsVarArg, MF, ArgLocs, Ctx);  in isEligibleForTailCallOptimization()  local
3589   CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForCall(CalleeCC, IsVarArg));  in isEligibleForTailCallOptimization()
3595   if (CCInfo.getStackSize() > FuncInfo->getBytesInStackArgArea())  in isEligibleForTailCallOptimization()
3704   CCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext());  in LowerCall()  local
3709     passSpecialInputs(CLI, CCInfo, *Info, RegsToPass, MemOpChains, Chain);  in LowerCall()
3712   CCInfo.AnalyzeCallOperands(Outs, AssignFn);  in LowerCall()
3715   unsigned NumBytes = CCInfo.getStackSize();  in LowerCall()