1132 // Peek through TFE struct returns to only use the data size.
1140   // TFE intrinsics return an aggregate type.  in memVTFromLoadIntrReturn()
7849 static bool parseTexFail(SDValue TexFailCtrl, SelectionDAG &DAG, SDValue *TFE,  in parseTexFail()  argument
7859   *TFE = DAG.getTargetConstant((Value & 0x1) ? 1 : 0, DL, MVT::i32);  in parseTexFail()
8122   SDValue TFE;  in lowerImage()  local
8126   if (!parseTexFail(TexFail, DAG, &TFE, &LWE, IsTexFail))  in lowerImage()
8198     Ops.push_back(TFE); //tfe  in lowerImage()
8199   } else if (TFE->getAsZExtVal()) {  in lowerImage()
8200     report_fatal_error("TFE is not supported on this GPU");  in lowerImage()
9355 // dwordx4 if on SI and handle TFE loads.
14812   case AMDGPU::sub4: return 4; // Possible with TFE/LWE  in SubIdx2Lane()
14831   unsigned TFEIdx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::tfe) - 1;  in adjustWritemask()
14846   // Work out which is the TFE/LWE lane if that is enabled.  in adjustWritemask()
14872     // Check if the use is for the TFE/LWE generated result at VGPRn+1.  in adjustWritemask()
14911   // Check for TFE or LWE - increase the number of channels by one to account  in adjustWritemask()
15115 // Any MIMG instructions that use tfe or lwe require an initialization of the
15130     MachineOperand *TFE = TII->getNamedOperand(MI, AMDGPU::OpName::tfe);  in AddMemOpInit()  local
15134     if (!TFE && !LWE) // intersect_ray  in AddMemOpInit()
15137     unsigned TFEVal = TFE ? TFE->getImm() : 0;  in AddMemOpInit()
15144     // At least one of TFE or LWE are non-zero  in AddMemOpInit()