149       STI.hasFeature(AMDGPU::FeatureInv2PiInlineImm))  in getLit16Encoding()
206       STI.hasFeature(AMDGPU::FeatureInv2PiInlineImm))  in getLit32Encoding()
246       STI.hasFeature(AMDGPU::FeatureInv2PiInlineImm))  in getLit64Encoding()
274   case AMDGPU::OPERAND_REG_IMM_INT32:  in getLitEncoding()
275   case AMDGPU::OPERAND_REG_IMM_FP32:  in getLitEncoding()
276   case AMDGPU::OPERAND_REG_IMM_FP32_DEFERRED:  in getLitEncoding()
277   case AMDGPU::OPERAND_REG_INLINE_C_INT32:  in getLitEncoding()
278   case AMDGPU::OPERAND_REG_INLINE_C_FP32:  in getLitEncoding()
279   case AMDGPU::OPERAND_REG_INLINE_AC_INT32:  in getLitEncoding()
280   case AMDGPU::OPERAND_REG_INLINE_AC_FP32:  in getLitEncoding()
281   case AMDGPU::OPERAND_REG_IMM_V2INT32:  in getLitEncoding()
282   case AMDGPU::OPERAND_REG_IMM_V2FP32:  in getLitEncoding()
283   case AMDGPU::OPERAND_REG_INLINE_C_V2INT32:  in getLitEncoding()
284   case AMDGPU::OPERAND_REG_INLINE_C_V2FP32:  in getLitEncoding()
285   case AMDGPU::OPERAND_INLINE_SPLIT_BARRIER_INT32:  in getLitEncoding()
288   case AMDGPU::OPERAND_REG_IMM_INT64:  in getLitEncoding()
289   case AMDGPU::OPERAND_REG_IMM_FP64:  in getLitEncoding()
290   case AMDGPU::OPERAND_REG_INLINE_C_INT64:  in getLitEncoding()
291   case AMDGPU::OPERAND_REG_INLINE_C_FP64:  in getLitEncoding()
292   case AMDGPU::OPERAND_REG_INLINE_AC_FP64:  in getLitEncoding()
295   case AMDGPU::OPERAND_REG_IMM_INT16:  in getLitEncoding()
296   case AMDGPU::OPERAND_REG_INLINE_C_INT16:  in getLitEncoding()
297   case AMDGPU::OPERAND_REG_INLINE_AC_INT16:  in getLitEncoding()
300   case AMDGPU::OPERAND_REG_IMM_FP16:  in getLitEncoding()
301   case AMDGPU::OPERAND_REG_IMM_FP16_DEFERRED:  in getLitEncoding()
302   case AMDGPU::OPERAND_REG_INLINE_C_FP16:  in getLitEncoding()
303   case AMDGPU::OPERAND_REG_INLINE_AC_FP16:  in getLitEncoding()
308   case AMDGPU::OPERAND_REG_IMM_BF16:  in getLitEncoding()
309   case AMDGPU::OPERAND_REG_IMM_BF16_DEFERRED:  in getLitEncoding()
310   case AMDGPU::OPERAND_REG_INLINE_C_BF16:  in getLitEncoding()
311   case AMDGPU::OPERAND_REG_INLINE_AC_BF16:  in getLitEncoding()
316   case AMDGPU::OPERAND_REG_IMM_V2INT16:  in getLitEncoding()
317   case AMDGPU::OPERAND_REG_INLINE_C_V2INT16:  in getLitEncoding()
318   case AMDGPU::OPERAND_REG_INLINE_AC_V2INT16:  in getLitEncoding()
319     return AMDGPU::getInlineEncodingV2I16(static_cast<uint32_t>(Imm))  in getLitEncoding()
322   case AMDGPU::OPERAND_REG_IMM_V2FP16:  in getLitEncoding()
323   case AMDGPU::OPERAND_REG_INLINE_C_V2FP16:  in getLitEncoding()
324   case AMDGPU::OPERAND_REG_INLINE_AC_V2FP16:  in getLitEncoding()
325     return AMDGPU::getInlineEncodingV2F16(static_cast<uint32_t>(Imm))  in getLitEncoding()
328   case AMDGPU::OPERAND_REG_IMM_V2BF16:  in getLitEncoding()
329   case AMDGPU::OPERAND_REG_INLINE_C_V2BF16:  in getLitEncoding()
330   case AMDGPU::OPERAND_REG_INLINE_AC_V2BF16:  in getLitEncoding()
331     return AMDGPU::getInlineEncodingV2BF16(static_cast<uint32_t>(Imm))  in getLitEncoding()
334   case AMDGPU::OPERAND_KIMM32:  in getLitEncoding()
335   case AMDGPU::OPERAND_KIMM16:  in getLitEncoding()
343   using namespace AMDGPU::VOP3PEncoding;  in getImplicitOpSelHiEncoding()
344   using namespace AMDGPU::OpName;  in getImplicitOpSelHiEncoding()
346   if (AMDGPU::hasNamedOperand(Opcode, op_sel_hi)) {  in getImplicitOpSelHiEncoding()
347     if (AMDGPU::hasNamedOperand(Opcode, src2))  in getImplicitOpSelHiEncoding()
349     if (AMDGPU::hasNamedOperand(Opcode, src1))  in getImplicitOpSelHiEncoding()
351     if (AMDGPU::hasNamedOperand(Opcode, src0))  in getImplicitOpSelHiEncoding()
359          Desc.hasImplicitDefOfPhysReg(AMDGPU::EXEC);  in isVCMPX64()
375       Opcode == AMDGPU::V_ACCVGPR_READ_B32_vi ||  in encodeInstruction()
376       Opcode == AMDGPU::V_ACCVGPR_WRITE_B32_vi) {  in encodeInstruction()
386   if (AMDGPU::isGFX10Plus(STI) && isVCMPX64(Desc)) {  in encodeInstruction()
388     Encoding |= MRI.getEncodingValue(AMDGPU::EXEC_LO) &  in encodeInstruction()
389                 AMDGPU::HWEncoding::REG_IDX_MASK;  in encodeInstruction()
397   if (AMDGPU::isGFX10Plus(STI) && Desc.TSFlags & SIInstrFlags::MIMG) {  in encodeInstruction()
398     int vaddr0 = AMDGPU::getNamedOperandIdx(MI.getOpcode(),  in encodeInstruction()
399                                             AMDGPU::OpName::vaddr0);  in encodeInstruction()
400     int srsrc = AMDGPU::getNamedOperandIdx(MI.getOpcode(),  in encodeInstruction()
401                                            AMDGPU::OpName::srsrc);  in encodeInstruction()
414   if ((bytes > 8 && STI.hasFeature(AMDGPU::FeatureVOP3Literal)) ||  in encodeInstruction()
415       (bytes > 4 && !STI.hasFeature(AMDGPU::FeatureVOP3Literal)))  in encodeInstruction()
419   if (AMDGPU::hasNamedOperand(MI.getOpcode(), AMDGPU::OpName::imm))  in encodeInstruction()
426     if (!AMDGPU::isSISrcOperand(Desc, i))  in encodeInstruction()
446     if (Desc.operands()[i].OperandType == AMDGPU::OPERAND_REG_IMM_FP64)  in encodeInstruction()
464     MCFixupKind Kind = (MCFixupKind)AMDGPU::fixup_si_sopp_br;  in getSOPPBrEncoding()
477   assert(!AMDGPU::isVI(STI) || isUInt<20>(Offset));  in getSMEMOffsetEncoding()
485   using namespace AMDGPU::SDWA;  in getSDWASrcEncoding()
495     if (AMDGPU::isSGPR(AMDGPU::mc2PseudoReg(Reg), &MRI)) {  in getSDWASrcEncoding()
515   using namespace AMDGPU::SDWA;  in getSDWAVopcDstEncoding()
522   if (Reg != AMDGPU::VCC && Reg != AMDGPU::VCC_LO) {  in getSDWAVopcDstEncoding()
535   unsigned Idx = Enc & AMDGPU::HWEncoding::REG_IDX_MASK;  in getAVOperandEncoding()
536   bool IsVGPROrAGPR = Enc & AMDGPU::HWEncoding::IS_VGPR_OR_AGPR;  in getAVOperandEncoding()
542   if (MRI.getRegClass(AMDGPU::AGPR_32RegClassID).contains(Reg) ||  in getAVOperandEncoding()
543       MRI.getRegClass(AMDGPU::AReg_64RegClassID).contains(Reg) ||  in getAVOperandEncoding()
544       MRI.getRegClass(AMDGPU::AReg_96RegClassID).contains(Reg) ||  in getAVOperandEncoding()
545       MRI.getRegClass(AMDGPU::AReg_128RegClassID).contains(Reg) ||  in getAVOperandEncoding()
546       MRI.getRegClass(AMDGPU::AReg_160RegClassID).contains(Reg) ||  in getAVOperandEncoding()
547       MRI.getRegClass(AMDGPU::AReg_192RegClassID).contains(Reg) ||  in getAVOperandEncoding()
548       MRI.getRegClass(AMDGPU::AReg_224RegClassID).contains(Reg) ||  in getAVOperandEncoding()
549       MRI.getRegClass(AMDGPU::AReg_256RegClassID).contains(Reg) ||  in getAVOperandEncoding()
550       MRI.getRegClass(AMDGPU::AReg_288RegClassID).contains(Reg) ||  in getAVOperandEncoding()
551       MRI.getRegClass(AMDGPU::AReg_320RegClassID).contains(Reg) ||  in getAVOperandEncoding()
552       MRI.getRegClass(AMDGPU::AReg_352RegClassID).contains(Reg) ||  in getAVOperandEncoding()
553       MRI.getRegClass(AMDGPU::AReg_384RegClassID).contains(Reg) ||  in getAVOperandEncoding()
554       MRI.getRegClass(AMDGPU::AReg_512RegClassID).contains(Reg) ||  in getAVOperandEncoding()
555       MRI.getRegClass(AMDGPU::AGPR_LO16RegClassID).contains(Reg))  in getAVOperandEncoding()
590     unsigned Idx = Enc & AMDGPU::HWEncoding::REG_IDX_MASK;  in getMachineOpValue()
591     bool IsVGPR = Enc & AMDGPU::HWEncoding::IS_VGPR_OR_AGPR;  in getMachineOpValue()
605     unsigned Idx = Enc & AMDGPU::HWEncoding::REG_IDX_MASK;  in getMachineOpValueT16()
606     bool IsVGPR = Enc & AMDGPU::HWEncoding::IS_VGPR_OR_AGPR;  in getMachineOpValueT16()
617   if ((int)OpNo == AMDGPU::getNamedOperandIdx(MI.getOpcode(),  in getMachineOpValueT16()
618                                               AMDGPU::OpName::src0_modifiers)) {  in getMachineOpValueT16()
619     SrcMOIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::src0);  in getMachineOpValueT16()
621         AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vdst);  in getMachineOpValueT16()
624       if (AMDGPU::isHi(DstReg, MRI))  in getMachineOpValueT16()
627   } else if ((int)OpNo == AMDGPU::getNamedOperandIdx(  in getMachineOpValueT16()
628                               MI.getOpcode(), AMDGPU::OpName::src1_modifiers))  in getMachineOpValueT16()
629     SrcMOIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::src1);  in getMachineOpValueT16()
630   else if ((int)OpNo == AMDGPU::getNamedOperandIdx(  in getMachineOpValueT16()
631                             MI.getOpcode(), AMDGPU::OpName::src2_modifiers))  in getMachineOpValueT16()
632     SrcMOIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::src2);  in getMachineOpValueT16()
640   if (AMDGPU::isSGPR(SrcReg, &MRI))  in getMachineOpValueT16()
642   if (AMDGPU::isHi(SrcReg, MRI))  in getMachineOpValueT16()
652     unsigned RegIdx = Encoding & AMDGPU::HWEncoding::REG_IDX_MASK;  in getMachineOpValueT16Lo128()
653     bool IsHi = Encoding & AMDGPU::HWEncoding::IS_HI;  in getMachineOpValueT16Lo128()
654     bool IsVGPR = Encoding & AMDGPU::HWEncoding::IS_VGPR_OR_AGPR;  in getMachineOpValueT16Lo128()
696   if (AMDGPU::isSISrcOperand(Desc, OpNo)) {  in getMachineOpValueCommon()