Lines Matching refs:STI
44 StringRef Annot, const MCSubtargetInfo &STI, in printInst() argument
46 printInstruction(MI, Address, STI, OS); in printInst()
51 const MCSubtargetInfo &STI, in printU4ImmOperand() argument
57 const MCSubtargetInfo &STI, in printU16ImmOperand() argument
71 printU32ImmOperand(MI, OpNo, STI, O); in printU16ImmOperand()
90 const MCSubtargetInfo &STI, in printU32ImmOperand() argument
103 const MCSubtargetInfo &STI, in printOffset() argument
112 if (AMDGPU::isGFX12(STI) && IsVBuffer) in printOffset()
120 const MCSubtargetInfo &STI, in printFlatOffset() argument
129 AMDGPU::isGFX12(STI); in printFlatOffset()
132 O << formatDec(SignExtend32(Imm, AMDGPU::getNumFlatOffsetBits(STI))); in printFlatOffset()
139 const MCSubtargetInfo &STI, in printOffset0() argument
148 const MCSubtargetInfo &STI, in printOffset1() argument
157 const MCSubtargetInfo &STI, in printSMRDOffset8() argument
159 printU32ImmOperand(MI, OpNo, STI, O); in printSMRDOffset8()
163 const MCSubtargetInfo &STI, in printSMEMOffset() argument
169 const MCSubtargetInfo &STI, in printSMEMOffsetMod() argument
172 printSMEMOffset(MI, OpNo, STI, O); in printSMEMOffsetMod()
176 const MCSubtargetInfo &STI, in printSMRDLiteralOffset() argument
178 printU32ImmOperand(MI, OpNo, STI, O); in printSMRDLiteralOffset()
182 const MCSubtargetInfo &STI, raw_ostream &O) { in printCPol() argument
185 if (AMDGPU::isGFX12Plus(STI)) { in printCPol()
196 O << ((AMDGPU::isGFX940(STI) && in printCPol()
200 O << (AMDGPU::isGFX940(STI) ? " nt" : " slc"); in printCPol()
201 if ((Imm & CPol::DLC) && AMDGPU::isGFX10Plus(STI)) in printCPol()
203 if ((Imm & CPol::SCC) && AMDGPU::isGFX90A(STI)) in printCPol()
204 O << (AMDGPU::isGFX940(STI) ? " sc1" : " scc"); in printCPol()
293 const MCSubtargetInfo &STI, raw_ostream &O) { in printDMask() argument
296 printU16ImmOperand(MI, OpNo, STI, O); in printDMask()
301 const MCSubtargetInfo &STI, raw_ostream &O) { in printDim() argument
313 const MCSubtargetInfo &STI, raw_ostream &O) { in printR128A16() argument
314 if (STI.hasFeature(AMDGPU::FeatureR128A16)) in printR128A16()
321 const MCSubtargetInfo &STI, in printFORMAT() argument
326 const MCSubtargetInfo &STI, in printSymbolicFormat() argument
335 if (AMDGPU::isGFX10Plus(STI)) { in printSymbolicFormat()
338 if (isValidUnifiedFormat(Val, STI)) { in printSymbolicFormat()
339 O << " format:[" << getUnifiedFormatName(Val, STI) << ']'; in printSymbolicFormat()
346 if (isValidDfmtNfmt(Val, STI)) { in printSymbolicFormat()
358 O << getNfmtName(Nfmt, STI); in printSymbolicFormat()
386 const MCSubtargetInfo &STI, raw_ostream &O) { in printVOPDst() argument
405 printRegularOperand(MI, OpNo, STI, O); in printVOPDst()
441 printDefaultVccOperand(false, STI, O); in printVOPDst()
447 const MCSubtargetInfo &STI, raw_ostream &O) { in printVINTRPDst() argument
448 if (AMDGPU::isSI(STI) || AMDGPU::isCI(STI)) in printVINTRPDst()
453 printRegularOperand(MI, OpNo, STI, O); in printVINTRPDst()
457 const MCSubtargetInfo &STI, in printImmediateInt16() argument
465 if (printImmediateFloat32(Imm, STI, O)) in printImmediateInt16()
471 static bool printImmediateFP16(uint32_t Imm, const MCSubtargetInfo &STI, in printImmediateFP16() argument
489 else if (Imm == 0x3118 && STI.hasFeature(AMDGPU::FeatureInv2PiInlineImm)) in printImmediateFP16()
497 static bool printImmediateBFloat16(uint32_t Imm, const MCSubtargetInfo &STI, in printImmediateBFloat16() argument
515 else if (Imm == 0x3E22 && STI.hasFeature(AMDGPU::FeatureInv2PiInlineImm)) in printImmediateBFloat16()
524 const MCSubtargetInfo &STI, in printImmediateBF16() argument
532 if (printImmediateBFloat16(static_cast<uint16_t>(Imm), STI, O)) in printImmediateBF16()
539 const MCSubtargetInfo &STI, in printImmediateF16() argument
548 if (printImmediateFP16(HImm, STI, O)) in printImmediateF16()
556 const MCSubtargetInfo &STI, in printImmediateV216() argument
568 if (printImmediateFloat32(Imm, STI, O)) in printImmediateV216()
575 printImmediateFP16(static_cast<uint16_t>(Imm), STI, O)) in printImmediateV216()
582 printImmediateBFloat16(static_cast<uint16_t>(Imm), STI, O)) in printImmediateV216()
593 const MCSubtargetInfo &STI, in printImmediateFloat32() argument
614 STI.hasFeature(AMDGPU::FeatureInv2PiInlineImm)) in printImmediateFloat32()
623 const MCSubtargetInfo &STI, in printImmediate32() argument
631 if (printImmediateFloat32(Imm, STI, O)) in printImmediate32()
638 const MCSubtargetInfo &STI, in printImmediate64() argument
665 STI.hasFeature(AMDGPU::FeatureInv2PiInlineImm)) in printImmediate64()
680 const MCSubtargetInfo &STI, in printBLGP() argument
686 if (AMDGPU::isGFX940(STI)) { in printBLGP()
702 const MCSubtargetInfo &STI, in printCBSZ() argument
712 const MCSubtargetInfo &STI, in printABID() argument
722 const MCSubtargetInfo &STI, in printDefaultVccOperand() argument
726 printRegOperand(STI.hasFeature(AMDGPU::FeatureWavefrontSize64) in printDefaultVccOperand()
735 const MCSubtargetInfo &STI, in printWaitVDST() argument
742 const MCSubtargetInfo &STI, in printWaitVAVDst() argument
749 const MCSubtargetInfo &STI, in printWaitVMVSrc() argument
756 const MCSubtargetInfo &STI, in printWaitEXP() argument
773 const MCSubtargetInfo &STI, in printOperand() argument
786 printDefaultVccOperand(true, STI, O); in printOperand()
788 printRegularOperand(MI, OpNo, STI, O); in printOperand()
793 const MCSubtargetInfo &STI, in printRegularOperand() argument
834 printImmediate32(Op.getImm(), STI, O); in printRegularOperand()
838 printImmediate64(Op.getImm(), STI, O, false); in printRegularOperand()
843 printImmediate64(Op.getImm(), STI, O, true); in printRegularOperand()
848 printImmediateInt16(Op.getImm(), STI, O); in printRegularOperand()
854 printImmediateF16(Op.getImm(), STI, O); in printRegularOperand()
860 printImmediateBF16(Op.getImm(), STI, O); in printRegularOperand()
871 printImmediateV216(Op.getImm(), OpTy, STI, O); in printRegularOperand()
880 printImmediate32(Op.getImm(), STI, O); in printRegularOperand()
898 printImmediate32(llvm::bit_cast<uint32_t>((float)Value), STI, O); in printRegularOperand()
900 printImmediate64(llvm::bit_cast<uint64_t>(Value), STI, O, true); in printRegularOperand()
954 printDefaultVccOperand(OpNo == 0, STI, O); in printRegularOperand()
963 printSymbolicFormat(MI, STI, O); in printRegularOperand()
969 const MCSubtargetInfo &STI, in printOperandAndFPInputMods() argument
973 printDefaultVccOperand(true, STI, O); in printOperandAndFPInputMods()
997 printRegularOperand(MI, OpNo + 1, STI, O); in printOperandAndFPInputMods()
1015 printDefaultVccOperand(OpNo == 0, STI, O); in printOperandAndFPInputMods()
1022 const MCSubtargetInfo &STI, in printOperandAndIntInputMods() argument
1026 printDefaultVccOperand(true, STI, O); in printOperandAndIntInputMods()
1031 printRegularOperand(MI, OpNo + 1, STI, O); in printOperandAndIntInputMods()
1044 printDefaultVccOperand(OpNo == 0, STI, O); in printOperandAndIntInputMods()
1050 const MCSubtargetInfo &STI, in printDPP8() argument
1052 if (!AMDGPU::isGFX10Plus(STI)) in printDPP8()
1064 const MCSubtargetInfo &STI, in printDPPCtrl() argument
1094 if (AMDGPU::isGFX10Plus(STI)) { in printDPPCtrl()
1100 if (AMDGPU::isGFX10Plus(STI)) { in printDPPCtrl()
1106 if (AMDGPU::isGFX10Plus(STI)) { in printDPPCtrl()
1112 if (AMDGPU::isGFX10Plus(STI)) { in printDPPCtrl()
1122 if (AMDGPU::isGFX10Plus(STI)) { in printDPPCtrl()
1128 if (AMDGPU::isGFX10Plus(STI)) { in printDPPCtrl()
1135 if (AMDGPU::isGFX90A(STI)) { in printDPPCtrl()
1137 } else if (AMDGPU::isGFX10Plus(STI)) { in printDPPCtrl()
1147 if (!AMDGPU::isGFX10Plus(STI)) { in printDPPCtrl()
1159 const MCSubtargetInfo &STI, in printDppRowMask() argument
1162 printU4ImmOperand(MI, OpNo, STI, O); in printDppRowMask()
1166 const MCSubtargetInfo &STI, in printDppBankMask() argument
1169 printU4ImmOperand(MI, OpNo, STI, O); in printDppBankMask()
1173 const MCSubtargetInfo &STI, in printDppBoundCtrl() argument
1182 const MCSubtargetInfo &STI, raw_ostream &O) { in printDppFI() argument
1208 const MCSubtargetInfo &STI, in printSDWADstSel() argument
1215 const MCSubtargetInfo &STI, in printSDWASrc0Sel() argument
1222 const MCSubtargetInfo &STI, in printSDWASrc1Sel() argument
1229 const MCSubtargetInfo &STI, in printSDWADstUnused() argument
1244 const MCSubtargetInfo &STI, raw_ostream &O, in printExpSrcN() argument
1263 const MCSubtargetInfo &STI, in printExpSrc0() argument
1265 printExpSrcN(MI, OpNo, STI, O, 0); in printExpSrc0()
1269 const MCSubtargetInfo &STI, in printExpSrc1() argument
1271 printExpSrcN(MI, OpNo, STI, O, 1); in printExpSrc1()
1275 const MCSubtargetInfo &STI, in printExpSrc2() argument
1277 printExpSrcN(MI, OpNo, STI, O, 2); in printExpSrc2()
1281 const MCSubtargetInfo &STI, in printExpSrc3() argument
1283 printExpSrcN(MI, OpNo, STI, O, 3); in printExpSrc3()
1287 const MCSubtargetInfo &STI, in printExpTgt() argument
1296 if (getTgtName(Id, TgtName, Index) && isSupportedTgtId(Id, STI)) { in printExpTgt()
1387 const MCSubtargetInfo &STI, in printOpSel() argument
1414 const MCSubtargetInfo &STI, in printOpSelHi() argument
1420 const MCSubtargetInfo &STI, in printNegLo() argument
1426 const MCSubtargetInfo &STI, in printNegHi() argument
1432 const MCSubtargetInfo &STI, in printIndexKey8bit() argument
1442 const MCSubtargetInfo &STI, in printIndexKey16bit() argument
1452 const MCSubtargetInfo &STI, in printInterpSlot() argument
1471 const MCSubtargetInfo &STI, in printInterpAttr() argument
1478 const MCSubtargetInfo &STI, in printInterpAttrChan() argument
1485 const MCSubtargetInfo &STI, in printGPRIdxMode() argument
1508 const MCSubtargetInfo &STI, in printMemOperand() argument
1510 printRegularOperand(MI, OpNo, STI, O); in printMemOperand()
1512 printRegularOperand(MI, OpNo + 1, STI, O); in printMemOperand()
1536 const MCSubtargetInfo &STI, in printOModSI() argument
1548 const MCSubtargetInfo &STI, in printSendMsg() argument
1557 decodeMsg(Imm16, MsgId, OpId, StreamId, STI); in printSendMsg()
1559 StringRef MsgName = getMsgName(MsgId, STI); in printSendMsg()
1561 if (!MsgName.empty() && isValidMsgOp(MsgId, OpId, STI) && in printSendMsg()
1562 isValidMsgStream(MsgId, OpId, StreamId, STI)) { in printSendMsg()
1564 if (msgRequiresOp(MsgId, STI)) { in printSendMsg()
1565 O << ", " << getMsgOpName(MsgId, OpId, STI); in printSendMsg()
1566 if (msgSupportsStream(MsgId, OpId, STI)) { in printSendMsg()
1612 const MCSubtargetInfo &STI, in printSwizzle() argument
1682 const MCSubtargetInfo &STI, in printSWaitCnt() argument
1684 AMDGPU::IsaVersion ISA = AMDGPU::getIsaVersion(STI.getCPU()); in printSWaitCnt()
1717 const MCSubtargetInfo &STI, in printDepCtr() argument
1724 if (isSymbolicDepCtrEncoding(Imm16, HasNonDefaultVal, STI)) { in printDepCtr()
1730 while (decodeDepCtr(Imm16, Id, Name, Val, IsDefault, STI)) { in printDepCtr()
1744 const MCSubtargetInfo &STI, in printSDelayALU() argument
1787 const MCSubtargetInfo &STI, raw_ostream &O) { in printHwreg() argument
1791 StringRef HwRegName = getHwreg(Id, STI); in printHwreg()
1805 const MCSubtargetInfo &STI, in printEndpgm() argument
1816 const MCSubtargetInfo &STI, in printByteSel() argument