Lines Matching refs:AMDGPU
25 using namespace llvm::AMDGPU;
112 if (AMDGPU::isGFX12(STI) && IsVBuffer) in printOffset()
129 AMDGPU::isGFX12(STI); in printFlatOffset()
132 O << formatDec(SignExtend32(Imm, AMDGPU::getNumFlatOffsetBits(STI))); in printFlatOffset()
185 if (AMDGPU::isGFX12Plus(STI)) { in printCPol()
196 O << ((AMDGPU::isGFX940(STI) && in printCPol()
200 O << (AMDGPU::isGFX940(STI) ? " nt" : " slc"); in printCPol()
201 if ((Imm & CPol::DLC) && AMDGPU::isGFX10Plus(STI)) in printCPol()
203 if ((Imm & CPol::SCC) && AMDGPU::isGFX90A(STI)) in printCPol()
204 O << (AMDGPU::isGFX940(STI) ? " sc1" : " scc"); in printCPol()
225 if (TH & AMDGPU::CPol::TH_ATOMIC_CASCADE) { in printTH()
226 if (Scope >= AMDGPU::CPol::SCOPE_DEV) in printTH()
227 O << "CASCADE" << (TH & AMDGPU::CPol::TH_ATOMIC_NT ? "_NT" : "_RT"); in printTH()
230 } else if (TH & AMDGPU::CPol::TH_ATOMIC_NT) in printTH()
231 O << "NT" << (TH & AMDGPU::CPol::TH_ATOMIC_RETURN ? "_RETURN" : ""); in printTH()
232 else if (TH & AMDGPU::CPol::TH_ATOMIC_RETURN) in printTH()
237 if (!IsStore && TH == AMDGPU::CPol::TH_RESERVED) in printTH()
245 case AMDGPU::CPol::TH_NT: in printTH()
248 case AMDGPU::CPol::TH_HT: in printTH()
251 case AMDGPU::CPol::TH_BYPASS: // or LU or RT_WB in printTH()
252 O << (Scope == AMDGPU::CPol::SCOPE_SYS ? "BYPASS" in printTH()
255 case AMDGPU::CPol::TH_NT_RT: in printTH()
258 case AMDGPU::CPol::TH_RT_NT: in printTH()
261 case AMDGPU::CPol::TH_NT_HT: in printTH()
264 case AMDGPU::CPol::TH_NT_WB: in printTH()
305 const AMDGPU::MIMGDimInfo *DimInfo = AMDGPU::getMIMGDimInfoByEncoding(Dim); in printDim()
314 if (STI.hasFeature(AMDGPU::FeatureR128A16)) in printR128A16()
328 using namespace llvm::AMDGPU::MTBUFFormat; in printSymbolicFormat()
331 AMDGPU::getNamedOperandIdx(MI->getOpcode(), AMDGPU::OpName::format); in printSymbolicFormat()
335 if (AMDGPU::isGFX10Plus(STI)) { in printSymbolicFormat()
371 case AMDGPU::FP_REG: in printRegOperand()
372 case AMDGPU::SP_REG: in printRegOperand()
373 case AMDGPU::PRIVATE_RSRC_REG: in printRegOperand()
375 case AMDGPU::SCC: in printRegOperand()
411 case AMDGPU::V_ADD_CO_CI_U32_e32_gfx10: in printVOPDst()
412 case AMDGPU::V_SUB_CO_CI_U32_e32_gfx10: in printVOPDst()
413 case AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx10: in printVOPDst()
414 case AMDGPU::V_ADD_CO_CI_U32_sdwa_gfx10: in printVOPDst()
415 case AMDGPU::V_SUB_CO_CI_U32_sdwa_gfx10: in printVOPDst()
416 case AMDGPU::V_SUBREV_CO_CI_U32_sdwa_gfx10: in printVOPDst()
417 case AMDGPU::V_ADD_CO_CI_U32_dpp_gfx10: in printVOPDst()
418 case AMDGPU::V_SUB_CO_CI_U32_dpp_gfx10: in printVOPDst()
419 case AMDGPU::V_SUBREV_CO_CI_U32_dpp_gfx10: in printVOPDst()
420 case AMDGPU::V_ADD_CO_CI_U32_dpp8_gfx10: in printVOPDst()
421 case AMDGPU::V_SUB_CO_CI_U32_dpp8_gfx10: in printVOPDst()
422 case AMDGPU::V_SUBREV_CO_CI_U32_dpp8_gfx10: in printVOPDst()
423 case AMDGPU::V_ADD_CO_CI_U32_e32_gfx11: in printVOPDst()
424 case AMDGPU::V_SUB_CO_CI_U32_e32_gfx11: in printVOPDst()
425 case AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx11: in printVOPDst()
426 case AMDGPU::V_ADD_CO_CI_U32_dpp_gfx11: in printVOPDst()
427 case AMDGPU::V_SUB_CO_CI_U32_dpp_gfx11: in printVOPDst()
428 case AMDGPU::V_SUBREV_CO_CI_U32_dpp_gfx11: in printVOPDst()
429 case AMDGPU::V_ADD_CO_CI_U32_dpp8_gfx11: in printVOPDst()
430 case AMDGPU::V_SUB_CO_CI_U32_dpp8_gfx11: in printVOPDst()
431 case AMDGPU::V_SUBREV_CO_CI_U32_dpp8_gfx11: in printVOPDst()
432 case AMDGPU::V_ADD_CO_CI_U32_e32_gfx12: in printVOPDst()
433 case AMDGPU::V_SUB_CO_CI_U32_e32_gfx12: in printVOPDst()
434 case AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx12: in printVOPDst()
435 case AMDGPU::V_ADD_CO_CI_U32_dpp_gfx12: in printVOPDst()
436 case AMDGPU::V_SUB_CO_CI_U32_dpp_gfx12: in printVOPDst()
437 case AMDGPU::V_SUBREV_CO_CI_U32_dpp_gfx12: in printVOPDst()
438 case AMDGPU::V_ADD_CO_CI_U32_dpp8_gfx12: in printVOPDst()
439 case AMDGPU::V_SUB_CO_CI_U32_dpp8_gfx12: in printVOPDst()
440 case AMDGPU::V_SUBREV_CO_CI_U32_dpp8_gfx12: in printVOPDst()
448 if (AMDGPU::isSI(STI) || AMDGPU::isCI(STI)) in printVINTRPDst()
489 else if (Imm == 0x3118 && STI.hasFeature(AMDGPU::FeatureInv2PiInlineImm)) in printImmediateFP16()
515 else if (Imm == 0x3E22 && STI.hasFeature(AMDGPU::FeatureInv2PiInlineImm)) in printImmediateBFloat16()
565 case AMDGPU::OPERAND_REG_IMM_V2INT16: in printImmediateV216()
566 case AMDGPU::OPERAND_REG_INLINE_C_V2INT16: in printImmediateV216()
567 case AMDGPU::OPERAND_REG_INLINE_AC_V2INT16: in printImmediateV216()
571 case AMDGPU::OPERAND_REG_IMM_V2FP16: in printImmediateV216()
572 case AMDGPU::OPERAND_REG_INLINE_C_V2FP16: in printImmediateV216()
573 case AMDGPU::OPERAND_REG_INLINE_AC_V2FP16: in printImmediateV216()
578 case AMDGPU::OPERAND_REG_IMM_V2BF16: in printImmediateV216()
579 case AMDGPU::OPERAND_REG_INLINE_C_V2BF16: in printImmediateV216()
580 case AMDGPU::OPERAND_REG_INLINE_AC_V2BF16: in printImmediateV216()
614 STI.hasFeature(AMDGPU::FeatureInv2PiInlineImm)) in printImmediateFloat32()
665 STI.hasFeature(AMDGPU::FeatureInv2PiInlineImm)) in printImmediate64()
668 assert(AMDGPU::isValid32BitLiteral(Imm, true)); in printImmediate64()
686 if (AMDGPU::isGFX940(STI)) { in printBLGP()
688 case AMDGPU::V_MFMA_F64_16X16X4F64_gfx940_acd: in printBLGP()
689 case AMDGPU::V_MFMA_F64_16X16X4F64_gfx940_vcd: in printBLGP()
690 case AMDGPU::V_MFMA_F64_4X4X4F64_gfx940_acd: in printBLGP()
691 case AMDGPU::V_MFMA_F64_4X4X4F64_gfx940_vcd: in printBLGP()
726 printRegOperand(STI.hasFeature(AMDGPU::FeatureWavefrontSize64) in printDefaultVccOperand()
727 ? AMDGPU::VCC in printDefaultVccOperand()
728 : AMDGPU::VCC_LO, in printDefaultVccOperand()
767 (Desc.hasImplicitDefOfPhysReg(AMDGPU::VCC) || in needsImpliedVcc()
768 Desc.hasImplicitDefOfPhysReg(AMDGPU::VCC_LO)); in needsImpliedVcc()
777 int ModIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0_modifiers); in printOperand()
784 (Desc.hasImplicitDefOfPhysReg(AMDGPU::VCC) || in printOperand()
785 Desc.hasImplicitDefOfPhysReg(AMDGPU::VCC_LO))) in printOperand()
821 case AMDGPU::OPERAND_REG_IMM_INT32: in printRegularOperand()
822 case AMDGPU::OPERAND_REG_IMM_FP32: in printRegularOperand()
823 case AMDGPU::OPERAND_REG_IMM_FP32_DEFERRED: in printRegularOperand()
824 case AMDGPU::OPERAND_REG_INLINE_C_INT32: in printRegularOperand()
825 case AMDGPU::OPERAND_REG_INLINE_C_FP32: in printRegularOperand()
826 case AMDGPU::OPERAND_REG_INLINE_AC_INT32: in printRegularOperand()
827 case AMDGPU::OPERAND_REG_INLINE_AC_FP32: in printRegularOperand()
828 case AMDGPU::OPERAND_REG_IMM_V2INT32: in printRegularOperand()
829 case AMDGPU::OPERAND_REG_IMM_V2FP32: in printRegularOperand()
830 case AMDGPU::OPERAND_REG_INLINE_C_V2INT32: in printRegularOperand()
831 case AMDGPU::OPERAND_REG_INLINE_C_V2FP32: in printRegularOperand()
833 case AMDGPU::OPERAND_INLINE_SPLIT_BARRIER_INT32: in printRegularOperand()
836 case AMDGPU::OPERAND_REG_IMM_INT64: in printRegularOperand()
837 case AMDGPU::OPERAND_REG_INLINE_C_INT64: in printRegularOperand()
840 case AMDGPU::OPERAND_REG_IMM_FP64: in printRegularOperand()
841 case AMDGPU::OPERAND_REG_INLINE_C_FP64: in printRegularOperand()
842 case AMDGPU::OPERAND_REG_INLINE_AC_FP64: in printRegularOperand()
845 case AMDGPU::OPERAND_REG_INLINE_C_INT16: in printRegularOperand()
846 case AMDGPU::OPERAND_REG_INLINE_AC_INT16: in printRegularOperand()
847 case AMDGPU::OPERAND_REG_IMM_INT16: in printRegularOperand()
850 case AMDGPU::OPERAND_REG_INLINE_C_FP16: in printRegularOperand()
851 case AMDGPU::OPERAND_REG_INLINE_AC_FP16: in printRegularOperand()
852 case AMDGPU::OPERAND_REG_IMM_FP16: in printRegularOperand()
853 case AMDGPU::OPERAND_REG_IMM_FP16_DEFERRED: in printRegularOperand()
856 case AMDGPU::OPERAND_REG_INLINE_C_BF16: in printRegularOperand()
857 case AMDGPU::OPERAND_REG_INLINE_AC_BF16: in printRegularOperand()
858 case AMDGPU::OPERAND_REG_IMM_BF16: in printRegularOperand()
859 case AMDGPU::OPERAND_REG_IMM_BF16_DEFERRED: in printRegularOperand()
862 case AMDGPU::OPERAND_REG_IMM_V2INT16: in printRegularOperand()
863 case AMDGPU::OPERAND_REG_IMM_V2BF16: in printRegularOperand()
864 case AMDGPU::OPERAND_REG_IMM_V2FP16: in printRegularOperand()
865 case AMDGPU::OPERAND_REG_INLINE_C_V2INT16: in printRegularOperand()
866 case AMDGPU::OPERAND_REG_INLINE_AC_V2INT16: in printRegularOperand()
867 case AMDGPU::OPERAND_REG_INLINE_C_V2BF16: in printRegularOperand()
868 case AMDGPU::OPERAND_REG_INLINE_C_V2FP16: in printRegularOperand()
869 case AMDGPU::OPERAND_REG_INLINE_AC_V2BF16: in printRegularOperand()
870 case AMDGPU::OPERAND_REG_INLINE_AC_V2FP16: in printRegularOperand()
896 unsigned RCBits = AMDGPU::getRegBitWidth(MRI.getRegClass(RCID)); in printRegularOperand()
915 case AMDGPU::V_CNDMASK_B32_e32_gfx10: in printRegularOperand()
916 case AMDGPU::V_ADD_CO_CI_U32_e32_gfx10: in printRegularOperand()
917 case AMDGPU::V_SUB_CO_CI_U32_e32_gfx10: in printRegularOperand()
918 case AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx10: in printRegularOperand()
919 case AMDGPU::V_ADD_CO_CI_U32_dpp_gfx10: in printRegularOperand()
920 case AMDGPU::V_SUB_CO_CI_U32_dpp_gfx10: in printRegularOperand()
921 case AMDGPU::V_SUBREV_CO_CI_U32_dpp_gfx10: in printRegularOperand()
922 case AMDGPU::V_CNDMASK_B32_dpp8_gfx10: in printRegularOperand()
923 case AMDGPU::V_ADD_CO_CI_U32_dpp8_gfx10: in printRegularOperand()
924 case AMDGPU::V_SUB_CO_CI_U32_dpp8_gfx10: in printRegularOperand()
925 case AMDGPU::V_SUBREV_CO_CI_U32_dpp8_gfx10: in printRegularOperand()
926 case AMDGPU::V_CNDMASK_B32_e32_gfx11: in printRegularOperand()
927 case AMDGPU::V_ADD_CO_CI_U32_e32_gfx11: in printRegularOperand()
928 case AMDGPU::V_SUB_CO_CI_U32_e32_gfx11: in printRegularOperand()
929 case AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx11: in printRegularOperand()
930 case AMDGPU::V_ADD_CO_CI_U32_dpp_gfx11: in printRegularOperand()
931 case AMDGPU::V_SUB_CO_CI_U32_dpp_gfx11: in printRegularOperand()
932 case AMDGPU::V_SUBREV_CO_CI_U32_dpp_gfx11: in printRegularOperand()
933 case AMDGPU::V_CNDMASK_B32_dpp8_gfx11: in printRegularOperand()
934 case AMDGPU::V_ADD_CO_CI_U32_dpp8_gfx11: in printRegularOperand()
935 case AMDGPU::V_SUB_CO_CI_U32_dpp8_gfx11: in printRegularOperand()
936 case AMDGPU::V_SUBREV_CO_CI_U32_dpp8_gfx11: in printRegularOperand()
937 case AMDGPU::V_CNDMASK_B32_e32_gfx12: in printRegularOperand()
938 case AMDGPU::V_ADD_CO_CI_U32_e32_gfx12: in printRegularOperand()
939 case AMDGPU::V_SUB_CO_CI_U32_e32_gfx12: in printRegularOperand()
940 case AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx12: in printRegularOperand()
941 case AMDGPU::V_CNDMASK_B32_dpp_gfx12: in printRegularOperand()
942 case AMDGPU::V_ADD_CO_CI_U32_dpp_gfx12: in printRegularOperand()
943 case AMDGPU::V_SUB_CO_CI_U32_dpp_gfx12: in printRegularOperand()
944 case AMDGPU::V_SUBREV_CO_CI_U32_dpp_gfx12: in printRegularOperand()
945 case AMDGPU::V_CNDMASK_B32_dpp8_gfx12: in printRegularOperand()
946 case AMDGPU::V_ADD_CO_CI_U32_dpp8_gfx12: in printRegularOperand()
947 case AMDGPU::V_SUB_CO_CI_U32_dpp8_gfx12: in printRegularOperand()
948 case AMDGPU::V_SUBREV_CO_CI_U32_dpp8_gfx12: in printRegularOperand()
950 case AMDGPU::V_CNDMASK_B32_e32_gfx6_gfx7: in printRegularOperand()
951 case AMDGPU::V_CNDMASK_B32_e32_vi: in printRegularOperand()
952 if ((int)OpNo == AMDGPU::getNamedOperandIdx(MI->getOpcode(), in printRegularOperand()
953 AMDGPU::OpName::src1)) in printRegularOperand()
960 AMDGPU::getNamedOperandIdx(MI->getOpcode(), AMDGPU::OpName::soffset); in printRegularOperand()
1010 case AMDGPU::V_CNDMASK_B32_sdwa_gfx10: in printOperandAndFPInputMods()
1011 case AMDGPU::V_CNDMASK_B32_dpp_gfx10: in printOperandAndFPInputMods()
1012 case AMDGPU::V_CNDMASK_B32_dpp_gfx11: in printOperandAndFPInputMods()
1014 AMDGPU::getNamedOperandIdx(MI->getOpcode(), AMDGPU::OpName::src1)) in printOperandAndFPInputMods()
1039 case AMDGPU::V_ADD_CO_CI_U32_sdwa_gfx10: in printOperandAndIntInputMods()
1040 case AMDGPU::V_SUB_CO_CI_U32_sdwa_gfx10: in printOperandAndIntInputMods()
1041 case AMDGPU::V_SUBREV_CO_CI_U32_sdwa_gfx10: in printOperandAndIntInputMods()
1042 if ((int)OpNo + 1 == AMDGPU::getNamedOperandIdx(MI->getOpcode(), in printOperandAndIntInputMods()
1043 AMDGPU::OpName::src1)) in printOperandAndIntInputMods()
1052 if (!AMDGPU::isGFX10Plus(STI)) in printDPP8()
1066 using namespace AMDGPU::DPP; in printDPPCtrl()
1071 if (!AMDGPU::isLegalDPALU_DPPControl(Imm) && AMDGPU::isDPALU_DPP(Desc)) { in printDPPCtrl()
1094 if (AMDGPU::isGFX10Plus(STI)) { in printDPPCtrl()
1100 if (AMDGPU::isGFX10Plus(STI)) { in printDPPCtrl()
1106 if (AMDGPU::isGFX10Plus(STI)) { in printDPPCtrl()
1112 if (AMDGPU::isGFX10Plus(STI)) { in printDPPCtrl()
1122 if (AMDGPU::isGFX10Plus(STI)) { in printDPPCtrl()
1128 if (AMDGPU::isGFX10Plus(STI)) { in printDPPCtrl()
1135 if (AMDGPU::isGFX90A(STI)) { in printDPPCtrl()
1137 } else if (AMDGPU::isGFX10Plus(STI)) { in printDPPCtrl()
1147 if (!AMDGPU::isGFX10Plus(STI)) { in printDPPCtrl()
1183 using namespace llvm::AMDGPU::DPP; in printDppFI()
1192 using namespace llvm::AMDGPU::SDWA; in printSDWASel()
1231 using namespace llvm::AMDGPU::SDWA; in printSDWADstUnused()
1247 int EnIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::en); in printExpSrcN()
1250 int ComprIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::compr); in printExpSrcN()
1289 using namespace llvm::AMDGPU::Exp; in printExpTgt()
1329 {AMDGPU::OpName::src0_modifiers, AMDGPU::OpName::src0}, in printPackedModifier()
1330 {AMDGPU::OpName::src1_modifiers, AMDGPU::OpName::src1}, in printPackedModifier()
1331 {AMDGPU::OpName::src2_modifiers, AMDGPU::OpName::src2}}; in printPackedModifier()
1335 if (!AMDGPU::hasNamedOperand(Opc, Src)) in printPackedModifier()
1338 int ModIdx = AMDGPU::getNamedOperandIdx(Opc, SrcMod); in printPackedModifier()
1350 {AMDGPU::OpName::src0_modifiers, AMDGPU::OpName::src1_modifiers, in printPackedModifier()
1351 AMDGPU::OpName::src2_modifiers}) { in printPackedModifier()
1352 int Idx = AMDGPU::getNamedOperandIdx(Opc, OpName); in printPackedModifier()
1392 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0_modifiers); in printOpSel()
1401 auto FIN = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0_modifiers); in printOpSel()
1402 auto BCN = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1_modifiers); in printOpSel()
1487 using namespace llvm::AMDGPU::VGPRIndexMode; in printGPRIdxMode()
1550 using namespace llvm::AMDGPU::SendMsg; in printSendMsg()
1582 using namespace llvm::AMDGPU::Swizzle; in printSwizzleBitmask()
1614 using namespace llvm::AMDGPU::Swizzle; in printSwizzle()
1684 AMDGPU::IsaVersion ISA = AMDGPU::getIsaVersion(STI.getCPU()); in printSWaitCnt()
1719 using namespace llvm::AMDGPU::DepCtr; in printDepCtr()
1788 using namespace llvm::AMDGPU::Hwreg; in printHwreg()