1 //===-- GCNPreRAOptimizations.cpp -----------------------------------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
25 //===----------------------------------------------------------------------===//
36 #define DEBUG_TYPE "amdgpu-pre-ra-optimizations"
47   bool processReg(Register Reg);
59     return "AMDGPU Pre-RA optimizations";  in getPassName()
72                       "AMDGPU Pre-RA optimizations", false, false)
74 INITIALIZE_PASS_END(GCNPreRAOptimizations, DEBUG_TYPE, "Pre-RA optimizations",
85 bool GCNPreRAOptimizations::processReg(Register Reg) {  in processReg()  argument
88   uint64_t Init = 0;  in processReg()  local
91   bool IsAGPRDst = TRI->isAGPRClass(MRI->getRegClass(Reg));  in processReg()
93   for (MachineInstr &I : MRI->def_instructions(Reg)) {  in processReg()
113       bool IsAGPRSrc = TRI->isAGPRClass(MRI->getRegClass(SrcReg));  in processReg()
121       for (auto &Def : MRI->def_instructions(SrcReg)) {  in processReg()
132             // Propagate source reg of accvgpr write to this copy instruction  in processReg()
136             // Reg uses were changed, collect unique set of registers to update  in processReg()
151       if (I.getOperand(0).getReg() != Reg || !I.getOperand(1).isImm() ||  in processReg()
162         Init |= I.getOperand(1).getImm() & 0xffffffff;  in processReg()
168         Init |= static_cast<uint64_t>(I.getOperand(1).getImm()) << 32;  in processReg()
175   // For AGPR reg, check if live intervals need to be updated.  in processReg()
179         LIS->removeInterval(RegToUpdate);  in processReg()
180         LIS->createAndComputeVirtRegInterval(RegToUpdate);  in processReg()
187   // For SGPR reg, check if we can combine instructions.  in processReg()
188   if (!Def0 || !Def1 || Def0->getParent() != Def1->getParent())  in processReg()
194   if (SlotIndex::isEarlierInstr(LIS->getInstructionIndex(*Def1),  in processReg()
195                                 LIS->getInstructionIndex(*Def0)))  in processReg()
198   LIS->RemoveMachineInstrFromMaps(*Def0);  in processReg()
199   LIS->RemoveMachineInstrFromMaps(*Def1);  in processReg()
200   auto NewI = BuildMI(*Def0->getParent(), *Def0, Def0->getDebugLoc(),  in processReg()
201                       TII->get(AMDGPU::S_MOV_B64_IMM_PSEUDO), Reg)  in processReg()
202                   .addImm(Init);  in processReg()
204   Def0->eraseFromParent();  in processReg()
205   Def1->eraseFromParent();  in processReg()
206   LIS->InsertMachineInstrInMaps(*NewI);  in processReg()
207   LIS->removeInterval(Reg);  in processReg()
208   LIS->createAndComputeVirtRegInterval(Reg);  in processReg()
227   for (unsigned I = 0, E = MRI->getNumVirtRegs(); I != E; ++I) {  in runOnMachineFunction()
228     Register Reg = Register::index2VirtReg(I);  in runOnMachineFunction()  local
229     if (!LIS->hasInterval(Reg))  in runOnMachineFunction()
231     const TargetRegisterClass *RC = MRI->getRegClass(Reg);  in runOnMachineFunction()
232     if ((RC->MC->getSizeInBits() != 64 || !TRI->isSGPRClass(RC)) &&  in runOnMachineFunction()
233         (ST.hasGFX90AInsts() || !TRI->isAGPRClass(RC)))  in runOnMachineFunction()
236     Changed |= processReg(Reg);  in runOnMachineFunction()