Lines Matching refs:TII
61 ST(MF.getSubtarget<GCNSubtarget>()), TII(*ST.getInstrInfo()), in GCNHazardRecognizer()
62 TRI(TII.getRegisterInfo()), TSchedModel(TII.getSchedModel()), in GCNHazardRecognizer()
119 static bool isSendMsgTraceDataOrGDS(const SIInstrInfo &TII, in isSendMsgTraceDataOrGDS() argument
121 if (TII.isAlwaysGDS(MI.getOpcode())) in isSendMsgTraceDataOrGDS()
135 if (TII.isDS(MI.getOpcode())) { in isSendMsgTraceDataOrGDS()
163 static unsigned getHWReg(const SIInstrInfo *TII, const MachineInstr &RegInstr) { in getHWReg() argument
164 const MachineOperand *RegOp = TII->getNamedOperand(RegInstr, in getHWReg()
221 (TII.isVINTRP(*MI) || isSMovRel(MI->getOpcode()) || in getHazardType()
224 (ST.hasReadM0SendMsgHazard() && isSendMsgTraceDataOrGDS(TII, *MI)) || in getHazardType()
244 static void insertNoopsInBundle(MachineInstr *MI, const SIInstrInfo &TII, in insertNoopsInBundle() argument
249 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), TII.get(AMDGPU::S_NOP)) in insertNoopsInBundle()
273 insertNoopsInBundle(CurrCycleInstr, TII, WaitStates); in processBundle()
294 insertNoopsInBundle(MI, TII, NumPreNoops); in runOnInstruction()
296 TII.insertNoops(*MI->getParent(), MachineBasicBlock::iterator(MI), in runOnInstruction()
361 (TII.isVINTRP(*MI) || isSMovRel(MI->getOpcode()) || in PreEmitNoopsCommon()
364 (ST.hasReadM0SendMsgHazard() && isSendMsgTraceDataOrGDS(TII, *MI)) || in PreEmitNoopsCommon()
399 unsigned NumWaitStates = TII.getNumWaitStates(*CurrCycleInstr); in AdvanceCycle()
610 bool IsSMRD = TII.isSMRD(*MEM); in checkSoftClauseHazards()
665 return TII.isVALU(MI); in checkSMRDHazards()
668 return TII.isSALU(MI); in checkSMRDHazards()
671 bool IsBufferSMRD = TII.isBufferSMRD(*SMRD); in checkSMRDHazards()
710 return TII.isVALU(MI); in checkVMEMHazards()
726 const SIInstrInfo *TII = ST.getInstrInfo(); in checkDPPHazards() local
732 auto IsHazardDefFn = [TII](const MachineInstr &MI) { in checkDPPHazards()
733 return TII->isVALU(MI); in checkDPPHazards()
756 const SIInstrInfo *TII = ST.getInstrInfo(); in checkDivFMasHazards() local
761 auto IsHazardDefFn = [TII](const MachineInstr &MI) { in checkDivFMasHazards()
762 return TII->isVALU(MI); in checkDivFMasHazards()
771 const SIInstrInfo *TII = ST.getInstrInfo(); in checkGetRegHazards() local
772 unsigned GetRegHWReg = getHWReg(TII, *GetRegInstr); in checkGetRegHazards()
775 auto IsHazardFn = [TII, GetRegHWReg](const MachineInstr &MI) { in checkGetRegHazards()
776 return GetRegHWReg == getHWReg(TII, MI); in checkGetRegHazards()
784 const SIInstrInfo *TII = ST.getInstrInfo(); in checkSetRegHazards() local
785 unsigned HWReg = getHWReg(TII, *SetRegInstr); in checkSetRegHazards()
788 auto IsHazardFn = [TII, HWReg](const MachineInstr &MI) { in checkSetRegHazards()
789 return HWReg == getHWReg(TII, MI); in checkSetRegHazards()
799 const SIInstrInfo *TII = ST.getInstrInfo(); in createsVALUHazard() local
808 if (TII->isMUBUF(MI) || TII->isMTBUF(MI)) { in createsVALUHazard()
816 TII->getNamedOperand(MI, AMDGPU::OpName::soffset); in createsVALUHazard()
828 if (TII->isMIMG(MI)) { in createsVALUHazard()
835 if (TII->isFLAT(MI)) { in createsVALUHazard()
884 const SIInstrInfo *TII = ST.getInstrInfo(); in getDstSelForwardingOperand() local
896 if (auto *DstSel = TII->getNamedOperand(MI, AMDGPU::OpName::dst_sel)) in getDstSelForwardingOperand()
898 return TII->getNamedOperand(MI, AMDGPU::OpName::vdst); in getDstSelForwardingOperand()
904 if (TII->getNamedImmOperand(MI, AMDGPU::OpName::src0_modifiers) & in getDstSelForwardingOperand()
906 return TII->getNamedOperand(MI, AMDGPU::OpName::vdst); in getDstSelForwardingOperand()
910 (TII->getNamedImmOperand(MI, AMDGPU::OpName::src2_modifiers) & in getDstSelForwardingOperand()
912 return TII->getNamedOperand(MI, AMDGPU::OpName::vdst); in getDstSelForwardingOperand()
918 return TII->getNamedOperand(MI, AMDGPU::OpName::vdst); in getDstSelForwardingOperand()
957 const SIInstrInfo *TII = ST.getInstrInfo(); in checkVALUHazards() local
958 Register Def = TII->getNamedOperand(MI, AMDGPU::OpName::vdst)->getReg(); in checkVALUHazards()
1041 MachineOperand *Src = TII.getNamedOperand(*VALU, AMDGPU::OpName::src0); in checkVALUHazards()
1138 const SIInstrInfo *TII = ST.getInstrInfo(); in checkRWLaneHazards() local
1143 TII->getNamedOperand(*RWLane, AMDGPU::OpName::src1); in checkRWLaneHazards()
1149 auto IsHazardFn = [TII](const MachineInstr &MI) { return TII->isVALU(MI); }; in checkRWLaneHazards()
1161 const SIInstrInfo *TII = ST.getInstrInfo(); in checkRFEHazards() local
1165 auto IsHazardFn = [TII](const MachineInstr &MI) { in checkRFEHazards()
1166 return getHWReg(TII, MI) == AMDGPU::Hwreg::ID_TRAPSTS; in checkRFEHazards()
1173 const SIInstrInfo *TII = ST.getInstrInfo(); in checkReadM0Hazards() local
1175 auto IsHazardFn = [TII](const MachineInstr &MI) { return TII->isSALU(MI); }; in checkReadM0Hazards()
1198 static bool isVCmpXWritesExec(const SIInstrInfo &TII, const SIRegisterInfo &TRI, in isVCmpXWritesExec() argument
1200 return (TII.isVOPC(MI) || in isVCmpXWritesExec()
1201 (MI.isCompare() && (TII.isVOP3(MI) || TII.isSDWA(MI)))) && in isVCmpXWritesExec()
1209 const SIInstrInfo *TII = ST.getInstrInfo(); in fixVcmpxPermlaneHazards() local
1211 auto IsHazardFn = [TII, TRI](const MachineInstr &MI) { in fixVcmpxPermlaneHazards()
1212 return isVCmpXWritesExec(*TII, *TRI, MI); in fixVcmpxPermlaneHazards()
1228 auto *Src0 = TII->getNamedOperand(*MI, AMDGPU::OpName::src0); in fixVcmpxPermlaneHazards()
1232 TII->get(AMDGPU::V_MOV_B32_e32)) in fixVcmpxPermlaneHazards()
1278 const SIInstrInfo *TII = ST.getInstrInfo(); in fixVMEMtoScalarWriteHazards() local
1280 TII->get(AMDGPU::S_WAITCNT_DEPCTR)) in fixVMEMtoScalarWriteHazards()
1304 const SIInstrInfo *TII = ST.getInstrInfo(); in fixSMEMtoVectorWriteHazards() local
1307 const MachineOperand *SDST = TII->getNamedOperand(*MI, SDSTName); in fixSMEMtoVectorWriteHazards()
1325 auto IsExpiredFn = [TII, IV](const MachineInstr &MI, int) { in fixSMEMtoVectorWriteHazards()
1326 if (TII->isSALU(MI)) { in fixSMEMtoVectorWriteHazards()
1347 if (TII->isSOPP(MI)) in fixSMEMtoVectorWriteHazards()
1367 TII->get(AMDGPU::S_MOV_B32), AMDGPU::SGPR_NULL) in fixSMEMtoVectorWriteHazards()
1390 const SIInstrInfo *TII = ST.getInstrInfo(); in fixVcmpxExecWARHazard() local
1391 auto IsExpiredFn = [TII, TRI](const MachineInstr &MI, int) { in fixVcmpxExecWARHazard()
1393 if (TII->getNamedOperand(MI, AMDGPU::OpName::sdst)) in fixVcmpxExecWARHazard()
1410 TII->get(AMDGPU::S_WAITCNT_DEPCTR)) in fixVcmpxExecWARHazard()
1491 const SIInstrInfo *TII = ST.getInstrInfo(); in fixLdsBranchVmemWARHazard() local
1493 TII->get(AMDGPU::S_WAITCNT_VSCNT)) in fixLdsBranchVmemWARHazard()
1505 const MachineOperand *VDST = TII.getNamedOperand(*MI, AMDGPU::OpName::vdst); in fixLdsDirectVALUHazard()
1538 TII.getNamedOperand(*MI, AMDGPU::OpName::waitvdst); in fixLdsDirectVALUHazard()
1548 const MachineOperand *VDST = TII.getNamedOperand(*MI, AMDGPU::OpName::vdst); in fixLdsDirectVMEMHazard()
1565 !TII.getNamedOperand(I, AMDGPU::OpName::waitvsrc)->getImm()); in fixLdsDirectVMEMHazard()
1573 TII.getNamedOperand(*MI, AMDGPU::OpName::waitvsrc)->setImm(0); in fixLdsDirectVMEMHazard()
1576 TII.get(AMDGPU::S_WAITCNT_DEPCTR)) in fixLdsDirectVMEMHazard()
1726 TII.get(AMDGPU::S_WAITCNT_DEPCTR)) in fixVALUPartialForwardingHazard()
1806 TII.get(AMDGPU::S_WAITCNT_DEPCTR)) in fixVALUTransUseHazard()
1816 const SIInstrInfo *TII = ST.getInstrInfo(); in fixWMMAHazards() local
1819 auto IsHazardFn = [MI, TII, TRI, this](const MachineInstr &I) { in fixWMMAHazards()
1826 TII->getNamedOperand(*MI, AMDGPU::OpName::src0)->getReg(); in fixWMMAHazards()
1828 TII->getNamedOperand(*MI, AMDGPU::OpName::src1)->getReg(); in fixWMMAHazards()
1831 TII->getNamedOperand(I, AMDGPU::OpName::vdst)->getReg(); in fixWMMAHazards()
1843 TII->getNamedOperand(*MI, AMDGPU::OpName::src2)->getReg(); in fixWMMAHazards()
1861 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), TII->get(AMDGPU::V_NOP_e32)); in fixWMMAHazards()
1880 MachineOperand *Amt = TII.getNamedOperand(*MI, AMDGPU::OpName::src0); in fixShift64HighRegBug()
1893 MachineOperand *Src1 = TII.getNamedOperand(*MI, AMDGPU::OpName::src1); in fixShift64HighRegBug()
1922 BuildMI(*MBB, MI, DL, TII.get(AMDGPU::S_WAITCNT)) in fixShift64HighRegBug()
1928 BuildMI(*MBB, MI, DL, TII.get(AMDGPU::V_SWAP_B32), NewAmtLo) in fixShift64HighRegBug()
1932 runOnInstruction(BuildMI(*MBB, MI, DL, TII.get(AMDGPU::V_SWAP_B32), NewAmt) in fixShift64HighRegBug()
1939 BuildMI(*MBB, std::next(MI->getIterator()), DL, TII.get(AMDGPU::V_SWAP_B32), in fixShift64HighRegBug()
1945 BuildMI(*MBB, std::next(MI->getIterator()), DL, TII.get(AMDGPU::V_SWAP_B32), in fixShift64HighRegBug()
1978 const SIInstrInfo *TII = ST.getInstrInfo(); in checkNSAtoVMEMHazard() local
1979 const auto *Offset = TII->getNamedOperand(*MI, AMDGPU::OpName::offset); in checkNSAtoVMEMHazard()
1983 auto IsHazardFn = [TII](const MachineInstr &I) { in checkNSAtoVMEMHazard()
1988 TII->getInstSizeInBytes(I) >= 16; in checkNSAtoVMEMHazard()
2205 Register Reg = TII.getNamedOperand(MI, AMDGPU::OpName::src2)->getReg(); in checkMAIHazards908()
2376 if (!TII.isXDL(*MI)) in checkMAIHazards90A()
2384 if (!TII.isXDL(*MI)) in checkMAIHazards90A()
2390 if (TII.isXDL(*MI) && !TII.isXDL(*MI1)) in checkMAIHazards90A()
2394 TII.isXDL(*MI1) in checkMAIHazards90A()
2395 ? (TII.isXDL(*MI) in checkMAIHazards90A()
2449 TII.isXDL(*MI1) in checkMAIHazards90A()
2539 const SIInstrInfo *TII = ST.getInstrInfo(); in checkPermlaneHazards() local
2541 auto IsVCmpXWritesExecFn = [TII, TRI](const MachineInstr &MI) { in checkPermlaneHazards()
2542 return isVCmpXWritesExec(*TII, *TRI, MI); in checkPermlaneHazards()
2658 if (!TII.isVALU(MI) || !DGEMMAfterVALUWrite) in checkMAIVALUHazards()
2748 TII.isXDL(*MFMA) in checkMAIVALUHazards()
2835 TII.isXDL(*MFMA) in checkMAIVALUHazards()
2867 if (ST.hasGFX940Insts() && !TII.isXDL(MI)) in checkMAIVALUHazards()
2871 TII.getNamedOperand(MI, AMDGPU::OpName::src2); in checkMAIVALUHazards()
2979 const MachineOperand *SDSTOp = TII.getNamedOperand(*MI, AMDGPU::OpName::sdst); in fixVALUMaskWriteHazard()
3023 const MachineOperand *SSRCOp = TII.getNamedOperand(I, AMDGPU::OpName::src2); in fixVALUMaskWriteHazard()
3069 if (!TII.isInlineConstant(Op, OpInfo)) in fixVALUMaskWriteHazard()
3085 TII.get(AMDGPU::S_WAITCNT_DEPCTR)) in fixVALUMaskWriteHazard()
3095 const SIInstrInfo &TII) { in ensureEntrySetPrio() argument
3104 BuildMI(EntryMBB, EntryMBB.begin(), DebugLoc(), TII.get(AMDGPU::S_SETPRIO)) in ensureEntrySetPrio()
3141 return ensureEntrySetPrio(MF, NormalPriority, TII); in fixRequiredExportPriority()
3148 (It != MBB->begin() && TII.isEXP(*std::prev(It))); in fixRequiredExportPriority()
3155 if (!TII.isEXP(*MI)) in fixRequiredExportPriority()
3164 Changed = ensureEntrySetPrio(MF, NormalPriority, TII); in fixRequiredExportPriority()
3170 if (TII.isEXP(*NextMI)) in fixRequiredExportPriority()
3182 BuildMI(*MBB, NextMI, DL, TII.get(AMDGPU::S_SETPRIO)) in fixRequiredExportPriority()
3187 BuildMI(*MBB, NextMI, DL, TII.get(AMDGPU::S_WAITCNT_EXPCNT)) in fixRequiredExportPriority()
3192 BuildMI(*MBB, NextMI, DL, TII.get(AMDGPU::S_NOP)).addImm(0); in fixRequiredExportPriority()
3193 BuildMI(*MBB, NextMI, DL, TII.get(AMDGPU::S_NOP)).addImm(0); in fixRequiredExportPriority()
3197 BuildMI(*MBB, NextMI, DL, TII.get(AMDGPU::S_SETPRIO)) in fixRequiredExportPriority()