64                               RegSubRegPair CombOldVGPR,
69                               RegSubRegPair CombOldVGPR, bool CombBCZ,
207                                            RegSubRegPair CombOldVGPR,  in createDPPInst()  argument
258           CombOldVGPR,  in createDPPInst()
262       auto *Def = getVRegSubRegDef(CombOldVGPR, *MRI);  in createDPPInst()
263       DPPInst.addReg(CombOldVGPR.Reg, Def ? 0 : RegState::Undef,  in createDPPInst()
264                      CombOldVGPR.SubReg);  in createDPPInst()
486     MachineInstr &OrigMI, MachineInstr &MovMI, RegSubRegPair CombOldVGPR,  in createDPPInst()  argument
488   assert(CombOldVGPR.Reg);  in createDPPInst()
499     CombOldVGPR = getRegSubRegPair(*Src1);  in createDPPInst()
502     if (!isOfRegClass(CombOldVGPR, *RC, *MRI)) {  in createDPPInst()
507   return createDPPInst(OrigMI, MovMI, CombOldVGPR, CombBCZ, IsShrinkable);  in createDPPInst()
612   auto CombOldVGPR = getRegSubRegPair(*OldOpnd);  in combineDPPMov()  local
616     CombOldVGPR = RegSubRegPair(  in combineDPPMov()
619                              TII->get(AMDGPU::IMPLICIT_DEF), CombOldVGPR.Reg);  in combineDPPMov()
706       if (auto *DPPInst = createDPPInst(OrigMI, MovMI, CombOldVGPR,  in combineDPPMov()
719                 createDPPInst(*NewMI, MovMI, CombOldVGPR, OldOpndValue, CombBCZ,  in combineDPPMov()