Lines Matching refs:vdata

110   bits<10> vdata;
126   bits<1> acc = !if(ps.has_vdst, vdst{9}, !if(ps.has_data, vdata{9}, 0));
141   let Inst{47-40} = !if(ps.has_data, vdata{7-0}, ?);
176   bits<8> vdata; // vsrc
188   let Inst{62-55} = !if(ps.has_data, vdata{7-0}, ?);
232       (ins VGPR_32:$vaddr, getLdStRegisterOperand<vdataClass>.ret:$vdata, SReg_64:$saddr),
233       (ins VReg_64:$vaddr, getLdStRegisterOperand<vdataClass>.ret:$vdata)),
235   " $vaddr, $vdata"#!if(HasSaddr, !if(EnableSaddr, ", $saddr", ", off"), "")#"$offset$cpol"> {
320   !con(!if(EnableSaddr, (ins vdataClass:$vdata, SReg_64:$saddr), (ins vdataClass:$vdata)),
322   " $vdata, "#!if(EnableSaddr, "$saddr", "off")#"$offset$cpol"> {
411 … (ins vdata_op:$vdata, VGPR_32:$vaddr, SReg_32_XEXEC_HI:$saddr, flat_offset:$offset, CPol_0:$cpol),
413       (ins vdata_op:$vdata, SReg_32_XEXEC_HI:$saddr, flat_offset:$offset, CPol_0:$cpol),
415         (ins vdata_op:$vdata, VGPR_32:$vaddr, flat_offset:$offset, CPol_0:$cpol),
416         (ins vdata_op:$vdata, flat_offset:$offset, CPol_0:$cpol)))),
417 …" "#!if(EnableVaddr, "$vaddr", "off")#", $vdata, "#!if(EnableSaddr, "$saddr", "off")#"$offset$cpol…
534     (ins VReg_64:$vaddr, data_op:$vdata, flat_offset:$offset, CPol_0:$cpol),
535     " $vaddr, $vdata$offset$cpol">,
551     (ins VReg_64:$vaddr, data_op:$vdata, flat_offset:$offset, CPol_GLC1:$cpol),
552     " $vdst, $vaddr, $vdata$offset$cpol">,
581       (ins VReg_64:$vaddr, data_op:$vdata, flat_offset:$offset, CPol_0:$cpol),
582       " $vaddr, $vdata, off$offset$cpol">,
590       (ins VGPR_32:$vaddr, data_op:$vdata, SReg_64:$saddr, flat_offset:$offset, CPol_0:$cpol),
591       " $vaddr, $vdata, $saddr$offset$cpol">,
612         (ins VReg_64:$vaddr, data_op:$vdata, flat_offset:$offset, CPol_GLC1:$cpol),
613       " $vdst, $vaddr, $vdata, off$offset$cpol">,
621         (ins VGPR_32:$vaddr, data_op:$vdata, SReg_64:$saddr, flat_offset:$offset, CPol_GLC1:$cpol),
622       " $vdst, $vaddr, $vdata, $saddr$offset$cpol">,