85   int OpIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), Name);  in insertNamedMCOperand()
394     unsigned Opc = Inst.getOpcode();  in decodeAVLdSt()
456   assert(MI.getOpcode() == 0);  in tryDecodeInst()
524   const MCInstrDesc &Desc = MCII.get(MI.getOpcode());  in decodeImmOperands()
764   if (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::DPP) {  in getInstruction()
768     if (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VOP3P)  in getInstruction()
770     else if (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VOPC)  in getInstruction()
772     else if (AMDGPU::isVOPC64DPP(MI.getOpcode()))  in getInstruction()
774     else if (AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::dpp8) !=  in getInstruction()
777     else if (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VOP3)  in getInstruction()
783   if (AMDGPU::isMAC(MI.getOpcode())) {  in getInstruction()
789   if (MI.getOpcode() == AMDGPU::V_CVT_SR_BF8_F32_e64_dpp ||  in getInstruction()
790       MI.getOpcode() == AMDGPU::V_CVT_SR_FP8_F32_e64_dpp) {  in getInstruction()
796   if ((MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::DS) &&  in getInstruction()
801   if (MCII->get(MI.getOpcode()).TSFlags &  in getInstruction()
803     int CPolPos = AMDGPU::getNamedOperandIdx(MI.getOpcode(),  in getInstruction()
807           (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::IsAtomicRet) ?  in getInstruction()
818   if ((MCII->get(MI.getOpcode()).TSFlags &  in getInstruction()
823         AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::tfe);  in getInstruction()
831   if (MCII->get(MI.getOpcode()).TSFlags &  in getInstruction()
834         AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::swz);  in getInstruction()
842   if (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::MIMG) {  in getInstruction()
844         AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vaddr0);  in getInstruction()
846         AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::srsrc);  in getInstruction()
855             MCII->get(MI.getOpcode()).operands()[VAddrIdx].RegClass;  in getInstruction()
864   if (MCII->get(MI.getOpcode()).TSFlags &  in getInstruction()
868   if (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::EXP)  in getInstruction()
871   if (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VINTERP)  in getInstruction()
874   if (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::SDWA)  in getInstruction()
877   if (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::IsMAI)  in getInstruction()
880   int VDstIn_Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(),  in getInstruction()
883     int Tied = MCII->get(MI.getOpcode()).getOperandConstraint(VDstIn_Idx,  in getInstruction()
896   bool IsSOPK = MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::SOPK;  in getInstruction()
897   if (AMDGPU::hasNamedOperand(MI.getOpcode(), AMDGPU::OpName::imm) && !IsSOPK)  in getInstruction()
903   if ((MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VOP3) &&  in getInstruction()
904       MCII->get(MI.getOpcode()).hasImplicitDefOfPhysReg(AMDGPU::EXEC)) {  in getInstruction()
925   if (MI.getOpcode() == AMDGPU::V_INTERP_P10_F16_F32_inreg_t16_gfx11 ||  in convertVINTERPInst()
926       MI.getOpcode() == AMDGPU::V_INTERP_P10_F16_F32_inreg_fake16_gfx11 ||  in convertVINTERPInst()
927       MI.getOpcode() == AMDGPU::V_INTERP_P10_F16_F32_inreg_t16_gfx12 ||  in convertVINTERPInst()
928       MI.getOpcode() == AMDGPU::V_INTERP_P10_F16_F32_inreg_fake16_gfx12 ||  in convertVINTERPInst()
929       MI.getOpcode() == AMDGPU::V_INTERP_P10_RTZ_F16_F32_inreg_t16_gfx11 ||  in convertVINTERPInst()
930       MI.getOpcode() == AMDGPU::V_INTERP_P10_RTZ_F16_F32_inreg_fake16_gfx11 ||  in convertVINTERPInst()
931       MI.getOpcode() == AMDGPU::V_INTERP_P10_RTZ_F16_F32_inreg_t16_gfx12 ||  in convertVINTERPInst()
932       MI.getOpcode() == AMDGPU::V_INTERP_P10_RTZ_F16_F32_inreg_fake16_gfx12 ||  in convertVINTERPInst()
933       MI.getOpcode() == AMDGPU::V_INTERP_P2_F16_F32_inreg_t16_gfx11 ||  in convertVINTERPInst()
934       MI.getOpcode() == AMDGPU::V_INTERP_P2_F16_F32_inreg_fake16_gfx11 ||  in convertVINTERPInst()
935       MI.getOpcode() == AMDGPU::V_INTERP_P2_F16_F32_inreg_t16_gfx12 ||  in convertVINTERPInst()
936       MI.getOpcode() == AMDGPU::V_INTERP_P2_F16_F32_inreg_fake16_gfx12 ||  in convertVINTERPInst()
937       MI.getOpcode() == AMDGPU::V_INTERP_P2_RTZ_F16_F32_inreg_t16_gfx11 ||  in convertVINTERPInst()
938       MI.getOpcode() == AMDGPU::V_INTERP_P2_RTZ_F16_F32_inreg_fake16_gfx11 ||  in convertVINTERPInst()
939       MI.getOpcode() == AMDGPU::V_INTERP_P2_RTZ_F16_F32_inreg_t16_gfx12 ||  in convertVINTERPInst()
940       MI.getOpcode() == AMDGPU::V_INTERP_P2_RTZ_F16_F32_inreg_fake16_gfx12) {  in convertVINTERPInst()
950     if (AMDGPU::hasNamedOperand(MI.getOpcode(), AMDGPU::OpName::sdst))  in convertSDWAInst()
954     int SDst = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::sdst);  in convertSDWAInst()
991       AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::blgp);  in convertMAIInst()
996       AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::cbsz);  in convertMAIInst()
1002       AMDGPU::getMFMA_F8F6F4_WithFormatArgs(CBSZ, BLGP, MI.getOpcode());  in convertMAIInst()
1004       AdjustedRegClassOpcode->Opcode == MI.getOpcode())  in convertMAIInst()
1009       AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::src0);  in convertMAIInst()
1011       AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::src1);  in convertMAIInst()
1031   unsigned Opc = MI.getOpcode();  in collectVOPModifiers()
1058   const unsigned Opc = MI.getOpcode();  in convertTrue16OpSel()
1094   auto Opcode = MI.getOpcode();  in isMacDPP()
1113   assert(MI.getNumOperands() + 1 < MCII->get(MI.getOpcode()).getNumOperands());  in convertMacDPPInst()
1120   unsigned Opc = MI.getOpcode();  in convertDPP8Inst()
1123       AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vdst_in);  in convertDPP8Inst()
1152       AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vdst_in);  in convertVOP3DPPInst()
1156   unsigned Opc = MI.getOpcode();  in convertVOP3DPPInst()
1170   auto TSFlags = MCII->get(MI.getOpcode()).TSFlags;  in convertMIMGInst()
1172   int VDstIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(),  in convertMIMGInst()
1175   int VDataIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(),  in convertMIMGInst()
1178       AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vaddr0);  in convertMIMGInst()
1182   int RsrcIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), RsrcOpName);  in convertMIMGInst()
1183   int DMaskIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(),  in convertMIMGInst()
1186   int TFEIdx   = AMDGPU::getNamedOperandIdx(MI.getOpcode(),  in convertMIMGInst()
1188   int D16Idx   = AMDGPU::getNamedOperandIdx(MI.getOpcode(),  in convertMIMGInst()
1191   const AMDGPU::MIMGInfo *Info = AMDGPU::getMIMGInfo(MI.getOpcode());  in convertMIMGInst()
1211         AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::dim);  in convertMIMGInst()
1213         AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::a16);  in convertMIMGInst()
1320   unsigned Opc = MI.getOpcode();  in convertVOP3PDPPInst()
1348   unsigned Opc = MI.getOpcode();  in convertVOPCDPPInst()
1367   unsigned Opc = MI.getOpcode();  in convertVOPC64DPPInst()
1836       AMDGPU::getNamedOperandIdx(Inst.getOpcode(), AMDGPU::OpName::vdstX);  in decodeVOPDDstYOp()